Programa de Pós-Graduação em Engenharia Elétrica

O Programa de Pós-Graduação em Engenharia Elétrica – PPGEE, da Universidade Federal do Rio Grande do Sul – UFRGS, tem a satisfação de convidar a Comunidade Universitária para assistir à Defesa Pública da Tese de Doutorado do Mestre em Engenharia Elétrica PAULO CÉSAR COMASSETTO DE AGUIRRE, a realizar-se:

Data: 08/11/2019 – sexta-feira
Horário: 14h00min
Local: Salão de Eventos do Instituto Eletrotécnico da UFRGS (Av. Osvaldo Aranha, 103 – 1º andar – Campus Centro)

Banca Examinadora:

Prof. Dr. Luís Henrique de Carvalho Ferreira – Instituto de Engenharia de Sistemas e Tecnologias da Informação – PPGEE – UNIFEI (Relator)
Prof. Dr. Sérgio Bampi – PGMICRO – PPGC – UFRGS
Prof. Dr. Tiago Roberto Balen – PGMICRO – UFRGS
Prof. Dr. Gilson Inácio Wirth – PPGEE – UFRGS
Prof. Dr. Ivan Müller – PPGEE – UFRGS

Orientador: Prof. Dr. Altamiro Amadeu Susin – PPGEE-UFRGS

Título da tese: “DESIGN OF CONTINUOUS-TIME SIGMA-DELTA MODULATORS WITH INVERTER-BASED AMPLIFIERS FOR SUB-1V APPLICATIONS”

Abstract:

“Analog-to-digital converters (ADCs) are essential building blocks in applications ranging from electronic instrumentation to modern communication systems and devices for Internet-of-Things (IoT). These applications demand power-efficient and reliable circuits to extend battery life, and low-voltage operation capability to allow energy harvesting operated devices. One of the most suitable ADC topologies for low-voltage and low-power applications is the Sigma-Delta (SD) ADC, whose design bottleneck is the loop-filter low-voltage operational transconductance amplifiers (OTAs). This thesis presents the development of sub-1V continuous-time sigma-delta modulators (CT-SDMs) with inverterbased amplifiers. The state of the art of CT-SDMs with inverter-based amplifiers has been delimited, and two low-voltage CT-SDMs prototypes have been designed and experimentally characterized. The first prototype is a 0.6-V third-order single-bit CT-SDM with a single-amplifier resonator in the loop filter and a low-power structure to implement the feed forward coefficients and quantization to increase power efficiency. The proposed single-stage inverter-based OTA topology has a negative conductance cell for DC gain enhancement and uses an on-chip bulk-bias technique to control the output common-mode voltage and to mitigate PVT variations. A compensation technique to mitigate the effects of amplifier’s finite DC gain in the resonator transfer function is presented enabling the use of low-gain amplifiers (≤ 40 dB). The proposed modulator was fabricated in a 130-nm triple-well CMOS process with an active area of 0.232 mm2 and presented a peak SNR/SNDR of 69.04/59.43 dB and a DR of 74.2 dB for a 100-kHz signal bandwidth while consuming 89.50 μW. The second prototype is a power-efficient third-order CTSDM with three loop-filter integrators and a passive RC path to assist the first integrator amplifier. The proposed inverter-based OTA uses a bulk-based current mirror to provide its operating point and to reduce gain-bandwidth product (GBW) variations. The proposed modulator was fabricated in a 180-nm CMOS process with an active area of 0.36 mm2. The modulator loop filter operates with a supply voltage as low as 0.45 V while the digital circuitry operates at 0.6 V. The modulator power consumption is 28.72 μW. For a 50-kHz signal bandwidth, the measured peak SNR/SNDR is 71.24/70.64 dB and the achieved DR is 78.3 dB, leading to a Schreier figure-of-merit of 170.70 dB.
Keywords: Sigma-Delta Modulation, AD conversion, Low-Voltage, Integrated Circuit Design.”