Eventos

Título

Autor Principal

Evento

A COMPARISON ON DIFFERENT LAYOUT TOPOLOGIES FOR VOLATILE DYNAMIC FLIP-FLOPS FEEDBACK BRANCH

KLAUS HOLLER

A HIGHLY RELIABLE WEARABLE DEVICE FOR FALL DETECTION

JOAO CARLOS BRITTO FILHO

A MANAGEMENT TECHNIQUE FOR CONCURRENT ACCESS TO A RECONFIGURABLE ACCELERATOR

RAUL SILVEIRA SILVA

A 37 NW MOSFET-ONLY VOLTAGE REFERENCE IN 0.13 ΜM CMOS

VANESSA FURTADO DE LIMA

A 40 NW 32.7 KHZ CMOS RELAXATION OSCILLATOR WITH COMPARATOR OFFSET CANCELLATION FOR ULTRA-LOW POWER APPLICATIONS

WILLIAM TELES MEDEIROS

AN EFFICIENT N-BIT 8-2 ADDER COMPRESSOR WITH A CONSTANT INTERNAL CARRY PROPAGATION DELAY

THOMAS VAITSES FONTANARI

AN EFFICIENT NLMS-BASED VLSI ARCHITECTURE FOR ROBUST FECG EXTRACTION AND FHR PROCESSING

PATRICIA UCKER

ANALYZING THE SENSITIVITY OF GPU PIPELINE REGISTERS TO SINGLE EVENTS UPSETS

Josie Esteban Rodriguez Condia

CHARACTERIZATION OF ENCLOSED LAYOUT TRANSISTORS FOR ANALOG APPLICATIONS ON A130NM TECHNOLOGY

GUSTAVO PAZ PLATCHECK

CIRCUIT LEVEL DESIGN METHODS TO MITIGATE SOFT ERRORS

RICARDO AUGUSTO DA LUZ REIS

COMBINING M=2 MULTIPLIERS AND ADDER COMPRESSORS FOR POWER EFFICIENT RADIX-4 BUTTERFLY

GUILHERME DA COSTA FERREIRA

CONTRIBUTIONS TO OPENROAD FROM ABROAD

MATEUS PAIVA FOGACA

CONTRIBUTIONS TO OPENROAD FROM ABROAD: EXPERIENCES AND LEARNINGS

MATEUS PAIVA FOGACA

DEFENDING LIGHTWEIGHT VIRTUAL SWITCHES FROMCROSS-APP POISONING ATTACKS WITH VIFC

GUILHERME BUENO DE OLIVEIRA

DIGITAL-BASED ANALOG PROCESSING IN NANOSCALE CMOS ICS FOR IOT APPLICATIONS

PEDRO FILIPE LEITE CORREIA DE TOLEDO

ENERGY-EFFICIENT HAAR TRANSFORM ARCHITECTURES USING EFFICIENT ADDITION SCHEMES

SEIDEL, HENRIQUE

EVALUATING CELL LIBRARY SIZING METHODOLOGIES FOR ULTRA-LOW POWER NEAR-THRESHOLD OPERATION IN BULK CMOS

RODRIGO NOGUEIRA WUERDIG

EVALUATING SOFTWARE-BASED HARDENING TECHNIQUES FOR GENERAL-PURPOSE REGISTERS ON A GPGPU

MARCIO MACEDO GONCALVES

EVALUATING THE IMPACT OF IONIZING PARTICLES ON FINFET -BASED SRAMS WITH WEAK RESISTIVE DEFECTS

THIAGO SANTOS COPETTI

EVALUATION OF CACHE-BASED MEMORY HIERARCHY FOR HEVC VIDEO DECODING

GARRENLUS DE SOUZA

EXPLORING EFFICIENT ADDER COMPRESSORS FOR POWER-EFFICIENT SUM OF SQUARED DIFFERENCES DESIGN

MORGANA MACEDO AZEVEDO DA ROSA

EXPLORING NLMS AND IPNLMS ADAPTIVE FILTERING VLSI HARDWARE ARCHITECTURES FOR ROBUST EEG SIGNAL ARTIFACTS ELIMINATION

ANDREI BORGES LA ROSA

EXPLORING PARALLEL PROGRAMMING IN AUTOMATIC TEST PATTERN GENERATION

CLAYTON RODRIGUES FARIAS

FAST AND SCALABLE I/O PIN ASSIGNMENT WITH DIVIDE-AND-CONQUER AND HUNGARIAN MATCHING

VITOR VIANA BANDEIRA

FBM V2: A SIMPLE AND EVEN FASTER ALGORITHM FOR PLACEMENT LEGALIZATION

JORGE ALBERTO FERREIRA

GATE SIZING FOR POWER-DELAY OPTIMIZATION AT TRANSISTOR-LEVEL MONOLITHIC 3D-INTEGRATED CIRCUITS

JULIANO CAVINATO ZANELLI

HARDWARE ARCHITECTURE FOR THE REGULAR INTERPOLATION FILTER OF THE AV1 VIDEO CODING STANDARD

DAIANE FONSECA FREITAS

IMPROVING THE PARTIAL PRODUCT TREE COMPRESSION ON SIGNED RADIX-2 <SUP>M</SUP> PARALLEL MULTIPLIERS

LEANDRO MATEUS GIACOMINI ROCHA

INFLUENCE OF SAMPLING FREQUENCY ON TID RESPONSE OF SAR ADCS

BRUNO LAU DA COSTA

INVESTIGATING FLOATING-POINT IMPLEMENTATIONS IN A SOFTCORE GPU UNDER RADIATION-INDUCED FAULTS

MARCIO MACEDO GONCALVES

LEVERAGING QDI ROBUSTNESS TO SIMPLIFY THE DESIGN OF IOT CIRCUITS

MARCOS LUIGGI LEMOS SARTORI

LOW-VOLTAGE DYNAMIC COMPARATOR WITH BULK-DRIVEN FLOATING INVERTER AMPLIFIER

BRUNO CANAL

MCEA: A RESOURCE-AWARE MULTICORE CGRA ARCHITECTURE FOR THE EDGE

GUILHERME DOS SANTOS KOROL

METHODS FOR SUSCEPTIBILITY ANALYSIS OF LOGIC GATES IN THE PRESENCE OF SINGLE EVENT TRANSIENTS

RAFAEL BUDIM SCHVITTZ

MIRROR FULL ADDER SET SUSCEPTIBILITY ON 7NM FINFET TECHNOLOGY

RAFAEL NEVES DE MELLO OLIVEIRA

MITIGATION EFFECTS OF DECOUPLING CELLS ON FULL ADDERS PROCESS VARIABILITY

FABIO GUSTAVO ROSSATO GOMES DA SILVA

NON-LINEAR SHUNT REGULATOR WITH RF POWER DETECTOR FOR RFID APPLICATIONS

RAFAEL SANTIAGO CANTALICE

ON DEMOCRATIZING HARDWARE DESIGN: UFRGS/FURG CONTRIBUTIONS TO THE OPENROAD PROJECT

MATEUS PAIVA FOGACA

OPTIMIZING ITERATIVE-BASED DIVIDERS FOR AN EFFICIENT NATURAL LOGARITHM OPERATOR DESIGN

PATRICIA UCKER

OPTIMIZING THE MONTGOMERY MODULAR MULTIPLIER FOR A POWER- AND AREA-EFFICIENT HARDWARE ARCHITECTURE

MATEUS TERRIBELE LEME

PERFORMANCE AND VARIABILITY TRADE-OFFS OF CMOS PTAT GENERATOR TOPOLOGIES FOR VOLTAGE REFERENCE APPLICATIONS

VANESSA FURTADO DE LIMA

PIN ACCESS ALGORITHMS FOR DETAILED ROUTING

MARCELO FREIRE DANIGNO

PROS AND CONS OF ST AND SIG FINFET INVERTERS FOR LOW POWER DESIGNS

LEONARDO BARLETTE DE MORAES

RAT: A LIGHTWEIGHT SYSTEM-LEVEL SOFT ERROR MITIGATION TECHNIQUE

JONAS FOGLIARINI GAVA

REVIEW ON THE EVOLUTION OF LOW-POWER AND HIGHLY-LINEAR TIME-TO-DIGITAL CONVERTERS - TDC

LESLEY DA SILVA FERREIRA

ROBUSTNESS ANALYSIS IN SRAM BIT CELLS

CLEITON MAGANO MARQUES

SELECTIVE HARDENING METHOD TO QUICKLY ESTIMATE THE SET OF MOST CRITICAL LOGIC GATES

GLORIA DENISE CLARO DA SILVA

SIMPLE ESSAY TO ASSESS THE IMPACT OF DIFFERENT METHODS ON RELIABILITY ANALYSIS

GLORIA DENISE CLARO DA SILVA

SOFT ERROR RELIABILITY ASSESSMENT OF NEURAL NETWORKS ON RESOURCE-CONSTRAINED IOT DEVICES

GEANCARLO ABICH

SOFT ERROR RELIABILITY OF SRAM CELLS DURING THE THREE OPERATION STATES

CLEITON MAGANO MARQUES

THE RADIX-2 SQUARED MULTIPLIER

MORGANA MACEDO AZEVEDO DA ROSA

TIME DEPENDENT THRESHOLD VOLTAGE VARIABILITY DUE TO RANDOM TELEGRAPH NOISE

GILSON INACIO WIRTH

TOWARDS A NONVOLATILE IMPLEMENTATION OF NEANDER ? AN ACCUMULATOR BASED 8-BIT PROCESSOR

BRUNA BIANCHI CAGLIARI

ULTRA-LOW POWER RELAXATION OSCILLATORS SURVEY: DESIGN TRENDS AND CHALLENGES

WILLIAM TELES MEDEIROS

VLSI DESIGN OF TREE-BASED INFERENCE FOR LOW-POWER LEARNING APPLICATIONS

BRUNNO ALVES DE ABREU

WORK-FUNCTION FLUCTUATION IMPACT ON THE SET RESPONSE OF FINFET-BASED MAJORITY VOTERS

LEONARDO HEITICH BRENDLER

Título

Autor Principal

Evento

A COMPARATIVE STUDY BETWEEN FINFET AND CMOS-BASED SRAMS UNDER RESISTIVE DEFECTS

THIAGO SANTOS COPETTI

A COMPILER FOR AUTOMATIC SELECTION OF SUITABLE PROCESSING-IN-MEMORY INSTRUCTIONS

AHMED HAMEEZA

A SUB-1MA HIGHLY LINEAR INDUCTORLESS WIDEBAND LNA WITH LOW IP3 SENSITIVITY TO VARIABILITY FOR IOT APPLICATIONS

ARTHUR LIRANETO TORRES COSTA

A 0.3-1.2V SCHOTTKY-BASED CMOS ZTC VOLTAGE REFERENCES

PEDRO FILIPE LEITE CORREIA DE TOLEDO

A 130 NM CMOS LNA FOR SATELLITE APPLICATION

RENE MORENO TIMBO

A 300MV-SUPPLY, 2NW-POWER, 80PF-LOAD CMOS DIGITAL-BASED OTA FOR IOT INTERFACES

PEDRO FILIPE LEITE CORREIA DE TOLEDO

AND-INVERTER-GRAPH (AIG) REPRESENTATION OF LARGE DIGITAL CIRCUITS

AUGUSTO ANDRE SOUZA BERNDT

AUTOMATIC TRANSCRIPTION SYSTEM FOR DIATONIC HARMONICA RECORDINGS

FILIPE MACIEL LINS

CLIP CLUSTERING FOR EARLY LITHOGRAPHIC HOTSPOT CLASSIFICATION

ANDRE SALDANHA OLIVEIRA

COMPARING EXHAUSTIVE AND RANDOM FAULT INJECTION METHODS FOR CONFIGURATION MEMORY ON SRAM-BASED FPGAS

FABIO BENEVENUTI

CRYPTOGRAPHY BY SYNCHRONIZATION OF HOPFIELD NEURAL NETWORKS THAT SIMULATE CHAOTIC SIGNALS GENERATED BY THE HUMAN BODY

ELIAS DE ALMEIDA RAMOS

ELECTRICAL CHARACTERIZATION OF AL/PVA/NI AND AL/PVA/P3HT/NI CAPACITORS FOR ORGANIC ELECTRONICS APPLICATIONS

TAIZA APARECIDA NEVES

ELECTROMAGNETIC IMMUNITY TEST OF ANALOG-TO-DIGITAL INTERFACES OF A MIXED-SIGNAL PROGRAMMABLE SOC

LUIZ GUILHERME SOUZA DIAS

EVALUATING THE IMPACT OF ACCURACY RELAXATION IN THE RELIABILITY OF GPU REGISTER FILES

MARCIO MACEDO GONCALVES

EVALUATION OF COMPILERS EFFECTS ON OPENMP SOFT ERROR RESILIENCY

JONAS FOGLIARINI GAVA

EVALUATION OF LEGALIZATION ALGORITHMS

JORGE ALBERTO FERREIRA

EVALUATION OF SET UNDER PROCESS VARIABILITY ON FINFET MULTI-LEVEL DESIGN

LEONARDO HEITICH BRENDLER

EXPERIMENTAL APPLICATIONS ON SRAM-BASED FPGA FOR THE NANOSATC-BR2 SCIENTIFIC MISSION

FABIO BENEVENUTI

EXPLOITING APPROXIMATE COMPUTING FOR LOW-COST FAULT TOLERANT ARCHITECTURES

GENNARO SEVERINO RODRIGUES

EXPLORING SCHMITT TRIGGER CIRCUITS FOR PROCESS VARIABILITY MITIGATION

LEONARDO BARLETTE DE MORAES

FBM: A SIMPLE AND FAST ALGORITHM FOR PLACEMENT LEGALIZATION

JORGE ALBERTO FERREIRA

FINDING PLACEMENT-RELEVANT CLUSTERS WITH FAST MODULARITY-BASED CLUSTERING

MATEUS PAIVA FOGACA

FINFET VARIABILITY AND NEAR-THRESHOLD OPERATION: IMPACT ON FULL ADDERS DESIGN USING XOR BLOCKS

FABIO GUSTAVO ROSSATO GOMES DA SILVA

FINFET VARIABILITY AND NEAR-THRESHOLD OPERATION: IMPACT ON FULL ADDERS DESIGN USING XOR BLOCKS

FABIO GUSTAVO ROSSATO GOMES DA SILVA

FLEXIBLE TEMPERATURE-PRESSURE ORGANIC SENSOR

LUCAS PRATES MARTINS

HARD VIRTUALIZATION OF P4-BASED SWITCHES WITH VIRTP4

MATEUS SAQUETTI PEREIRA DE CARVALHO TIRONE

IMPROVING SELECTIVE FAULT TOLERANCE IN GPU REGISTER FILES BY RELAXING REGISTER CRITICALITY

MARCIO MACEDO GONCALVES

IMPROVING SOFTWARE-BASED TECHNIQUES FOR SOFT ERROR MITIGATION IN OOO SUPERSCALAR PROCESSORS

DOUGLAS MACIEL CARDOSO

LOW ENERGY AND PROCESS VARIABILITY ANALYSIS OVER FINFET SCHMITT TRIGGER DESIGN

LEONARDO BARLETTE DE MORAES

MAXIMIZING SIDE CHANNEL ATTACK-RESISTANCE AND ENERGY-EFFICIENCY OF THE STTL COMBINING MULTI-V <SUB>T</SUB> TRANSISTORS WITH CURRENT AND CAPACITANCE BALANCING

VITOR GONCALVES DE LIMA

MINIMUM ENERGY FINFET SCHMITT TRIGGER DESIGN CONSIDERING PROCESS VARIABILITY

LEONARDO BARLETTE DE MORAES

NBTI IN SIGE TRANSISTORS

GILSON INACIO WIRTH

NON-INTRUSIVE FAULT INJECTION TECHNIQUES FOR EFFICIENT SOFT ERROR VULNERABILITY ANALYSIS

VITOR VIANA BANDEIRA

PACKAGING DEVELOPMENT OF AN IMPLANTABLE INTRACRANIAL PRESSURE CATHETER

JEFERSON CARDOSO DO ROSARIO

POWER-AWARE PHASE ORIENTED RECONFIGURABLE ARCHITECTURE

GUILHERME DOS SANTOS KOROL

PROCESS VARIABILITY CHALLENGES FOR RADIATION MITIGATION TECHNIQUES ON 16NM

SAMUEL PRESA TOLEDO

PROPOSAL AND EVALUATION OF PIN ACCESS ALGORITHMS FOR DETAILED ROUTING

MARCELO FREIRE DANIGNO

REDUCTION OF NEURAL NETWORK CIRCUITS BY CONSTANT AND NEARLY CONSTANT SIGNAL PROPAGATION

AUGUSTO ANDRE SOUZA BERNDT

STABILITY OF PEROVSKITE AND TWO TERMINAL SI/PEROVSKITE TANDEM SOLAR CELLS UNDER REVERSE BIAS

RICARDO AUGUSTO ZANOTTO RAZERA

TACKLING THE DRAWBACKS OF A LAGRANGIAN RELAXATION BASED DISCRETE GATE SIZING ALGORITHM

HENRIQUE PLACIDO

VARIABILITY ON CMOS VOLTAGE REFERENCES: A COMPARATIVE STUDY AND PERSPECTIVES

VANESSA FURTADO DE LIMA

VIRTP4: AN ARCHITECTURE FOR P4 VIRTUALIZATION

MATEUS SAQUETTI PEREIRA DE CARVALHO TIRONE

Título

Autor Principal

Evento

A DESIGN PATTERNS-BASED MIDDLEWARE FOR MULTIPROCESSOR SYSTEMS-ON-CHIP

JEAN CARLO HAMERSKI

A LOW-COST BRAM-BASED FUNCTION REUSE FOR CONFIGURABLE SOFT-CORE PROCESSORS IN FPGAS

PEDRO HENRIQUE EXENBERGER BECKER

A NONLINEAR PLACEMENT FOR FPGAS: THE CHAOTIC PLACE

ELIAS DE ALMEIDA RAMOS

A POLYPHONIC PITCH TRACKING EMBEDDED SYSTEM FOR RAPID INSTRUMENT AUGMENTATION

RODRIGO SCHRAMM

A 0.12-0.4 V, VERSATILE 3-TRANSISTOR CMOS VOLTAGE REFERENCE FOR ULTRA-LOW POWER SYSTEMS

ARTHUR CAMPOS DE OLIVEIRA

A 130 NM CMOS UHF SATELLITE RECEIVER FRONT-END FOR THE BRAZILIAN ENVIRONMENTAL DATA COLLECTING SYSTEM

RENE MORENO TIMBO

ADAPTIVE AND POLYMORPHIC VLIW PROCESSOR TO OPTIMIZE FAULT TOLERANCE, ENERGY CONSUMPTION, AND PERFORMANCE

ANDERSON LUIZ SARTOR

AN AUTOMATED METHODOLOGY TO FIX ELECTROMIGRATION VIOLATIONS ON A CUSTOMIZED DESIGN FLOW

LUCAS ANDRE DE PARIS

APPROXIMATE ON-THE-FLY COARSE-GRAINED RECONFIGURABLE ACCELERATION FOR GENERAL-PURPOSE APPLICATIONS

MARCELO BRANDALERO

ARFT: AN APPROXIMATIVE REDUNDANT TECHNIQUE FOR FAULT TOLERANCE

GENNARO SEVERINO RODRIGUES

AUTOMATED DESIGN FLOW FOR APPLYING TRIPLE MODULAR REDUNDANCY (TMR) IN COMPLEX DIGITAL CIRCUITS

LUIS ALBERTO CONTRERAS BENITES

CODE-DEPENDENT AND ARCHITECTURE-DEPENDENT RELIABILITY BEHAVIORS

VINICIUS FRATIN NETTO

DESIGN SPACE EXPLORATION FOR PIM ARCHITECTURES IN 3D-STACKED MEMORIES

JOAO PAULO CARDOSO DE LIMA

DIM-VEX: EXPLOITING DESIGN TIME CONFIGURABILITY AND RUNTIME RECONFIGURABILITY

JECKSON DELLAGOSTIN SOUZA

EARLY EVALUATION OF MULTICORE SYSTEMS SOFT ERROR RELIABILITY USING VIRTUAL PLATFORMS

FELIPE ROCHA DA ROSA

EMPLOYING CLASSIFICATION-BASED ALGORITHMS FOR GENERAL-PURPOSE APPROXIMATE COMPUTING

GERALDO FRANCISCO DE OLIVEIRA JUNIOR

EVALUATING THE IMPACT OF EXECUTION PARAMETERS ON PROGRAM VULNERABILITY IN GPU APPLICATIONS

Fritz Previlon

EVALUATING THE IMPACT OF PROCESS VARIABILITY AND RADIATION EFFECTS ON DIFFERENT TRANSISTOR ARRANGEMENT

LEONARDO HEITICH BRENDLER

EVALUATION OF COMPILER OPTIMIZATION FLAGS EFFECTS ON SOFT ERROR RESILIENCY

GUILHERME ESPINDOLA MEDEIROS

EXACT MULTI-LEVEL BENCHMARK CIRCUIT GENERATION FOR LOGIC SYNTHESIS EVALUATION

WALTER LAU NETO

EXACT MULTI-LEVEL LOGIC BENCHMARK GENERATION

WALTER LAU NETO

EXPLORING MULTI-LEVEL DESIGN TO MITIGATE VARIABILITY AND RADIATION EFFECTS ON 7NM FINFET LOGIC CELLS

LEONARDO HEITICH BRENDLER

EXPLORING POWER-PERFORMANCE-QUALITY TRADEOFF OF APPROXIMATE ADDERS FOR ENERGY EFFICIENT SOBEL FILTERING.

LEONARDO BANDEIRA SOARES

EXPLORING THE IMPACT OF SOFT ERRORS ON NOC-BASED MULTIPROCESSOR SYSTEMS

FELIPE TODESCHINI BORTOLON

EXPLORING THE INHERENT FAULT TOLERANCE OF SUCCESSIVE APPROXIMATION ALGORITHMS UNDER LASER FAULT INJECTION

GENNARO SEVERINO RODRIGUES

EXTENSIVE EVALUATION OF PROGRAMMING MODELS AND ISAS IMPACT ON MULTICORE SO ERROR RELIABILITY

FELIPE ROCHA DA ROSA

IMPROVING APPROXIMATE-TMR USING MULTI-OBJECTIVE OPTIMIZATION GENETIC ALGORITHM

IURI ALBANDES CUNHA GOMES

INFLUENCE OF TEMPERATURE ON DYNAMIC FAULT BEHAVIOR DUE TO RESISTIVE DEFECTS IN FINFET-BASED SRAMS

GUILHERME CARDOSO MEDEIROS

ISA-DTMR: SELECTIVE PROTECTION IN CONFIGURABLE HETEROGENEOUS MULTICORES

AUGUSTO GOSMANN ERICHSEN

LEARNING-BASED COMPLEXITY REDUCTION AND SCALING FOR HEVC ENCODERS

MATEUS GRELLERT DA SILVA

PARALLEL AIG REWRITING

VINICIUS NEVES POSSANI

PERFORMANCES VS RELIABILITY: HOW TO EXPLOIT APPROXIMATE COMPUTING FOR SAFETY-CRITICAL APPLICATIONS

GENNARO SEVERINO RODRIGUES

PRECISE EVALUATION OF THE FAULT SENSITIVITY OF OOO SUPERSCALAR PROCESSORS

RAFAEL BILLIG TONETTO

PREDICTING THE RELIABILITY BEHAVIOR OF HPC APPLICATIONS

DANIEL ALFONSO GONCALVES DE OLIVEIRA

PROCESSING IN 3D MEMORIES TO SPEED UP OPERATIONS ON COMPLEX DATA STRUCTURES

PAULO CESAR SANTOS DA SILVA JUNIOR

PROS AND CONS OF SCHMITT TRIGGER INVERTERS TO MITIGATE PVT VARIABILITY ON FULL ADDERS

SAMUEL PRESA TOLEDO

P3HT/PVA BASED ORGANIC FIELD-EFFECT TRANSISTORS

GABRIEL VOLKWEIS LEITE

REDUCING THE AMOUNT OF TRANSISTORS BY GATE MERGING

LUCIANA MENDES DA SILVA

REGISTER FILE SELECTIVE HARDENING FOR GRAPHICS PROCESSING UNITS

FERNANDO FERNANDES DOS SANTOS

RELIABILITY ANALYSIS ON CASE-STUDY TRAFFIC SIGN CONVOLUTIONAL NEURAL NETWORK ON APSOC

ISRAEL DA COSTA LOPES

RELIABILITY EVALUATION ON INTERFACING WITH AXI AND AXI-S ON XILINX ZYNQ-7000 AP-SOC

FABIO BENEVENUTI

SPECIAL SESSION: HOW APPROXIMATE COMPUTING IMPACTS VERIFICATION, TEST AND RELIABILITY

Lukas Sekanina

TECHNOLOGY MAPPING FOR CIRCUITS WITH SIMPLE CELLS

JODY MAICK ARAUJO DE MATOS

TIME DOMAIN ELECTRICAL CHARACTERIZATION IN ZINC OXIDE NANOPARTICLE THIN-FILM TRANSISTORS

THALES EXENBERGER BECKER

TOWARDS A VLSI DESIGN FLOW BASED ON LOGIC COMPUTATION AND SIGNAL DISTRIBUTION

ANDRE INACIO REIS

UNLOCKING FINE-GRAIN PARALLELISM FOR AIG REWRITING

VINICIUS NEVES POSSANI

WAKE-UP RECEIVERS SURVEY: DESIGN TRENDS AND CHALLENGES

NELSON JUNQUEIRA DE ANDRADE

Título

Autor Principal

Evento

A CELL CLUSTERING TECHNIQUE TO REDUCE TRANSISTOR COUNT

CALEBE MICAEL DE OLIVEIRA CONCEICAO

A COMPACT MODEL FOR BTI SIMULATION UNDER CYCLO-STATIONARY CONDITIONS

THIAGO HANNA BOTH

A FULLY INTEGRATED CMOS 2.4GHZ AND 24DBM LINEAR POWER AMPLIFIER

GABRIEL TEOFILO NEVES GUIMARAES

A HIGH IIP3 6.5 MW SELF-BIASED 0.3?3 GHZ SMALL AREA LNA

ARTHUR LIRANETO TORRES COSTA

A POWER-EFFICIENT 4-2 ADDER COMPRESSOR TOPOLOGY

RAPHAEL DORNELLES

A SUB-1 V, NANOPOWER, ZTC BASED ZERO-VT TEMPERATURE-COMPENSATED CURRENT REFERENCE

DAVID JAVIER CORDOVA VIVAS

A VARIABILITY-BASED ANALYSIS TECHNIQUE REVEALING PHYSICAL MECHANISMS OF MOSFET LOW-FREQUENCY NOISE

THIAGO HANNA BOTH

A 0.45 V, 93 PW TEMPERATURE-COMPENSATED CMOS VOLTAGE REFERENCE

ARTHUR CAMPOS DE OLIVEIRA

A 90% EFFICIENCY 60 MW MPPT SWITCHED CAPACITOR DC ? DC CONVERTER FOR PHOTOVOLTAIC ENERGY HARVESTING AIMING FOR IOT APPLICATIONS

ROGER LUIS BRITO ZAMPARETTE

AN ULTRA-LOW POWER HIGH-ORDER TEMPERATURE- COMPENSATED CMOS VOLTAGE REFERENCE

ARTHUR CAMPOS DE OLIVEIRA

ANALYZING LOCKSTEP DUAL-CORE ARM CORTEX-A9 SOFT ERROR MITIGATION IN FREERTOS APPLICATIONS

ADRIA BARROS DE OLIVEIRA

ANALYZING THE BEHAVIOR OF FINFET SRAMS WITH RESISTIVE DEFECTS

THIAGO SANTOS COPETTI

APPLYING LOCKSTEP IN DUAL-CORE ARM CORTEX-A9 TO MITIGATE RADIATION-INDUCED SOFT ERRORS

ADRIA BARROS DE OLIVEIRA

BINARY ADDER CIRCUIT DESIGN USING EMERGING MIGFET DEVICES

JEFERSON JOSE BAQUETA

DATA COMPRESSION AND DECOMPRESSION INTEGRATED CIRCUIT FOR AC POWER QUALITY DATA

MARCOS BARCELLOS HERVE

DETERMINISTIC METHODOLOGY TO EVALUATE BTI IMPACT ON LOGIC GATES PROPAGATION DELAY

GABRIELA FIRPO FURTADO

ELECTROMAGNETIC SIMULATION AND ANALYSIS OF CROSSTALK EFFECT IN INTEGRATED CIRCUITS

NELSON JUNQUEIRA DE ANDRADE

ENHANCING I2C ROBUSTNESS TO SOFT ERRORS

VICENTE BUENO CARVALHO

EVALUATING THE BEHAVIOR OF SUCCESSIVE APPROXIMATION ALGORITHMS UNDER SOFT ERRORS

GENNARO SEVERINO RODRIGUES

EVALUATING THE EFFICIENCY OF USING TMR IN THE HIGH-LEVEL SYNTHESIS DESIGN FLOW OF SRAM-BASED FPGA

ANDRE FLORES DOS SANTOS

EVALUATION OF A MIXED-SIGNAL DESIGN DIVERSITY SYSTEM UNDER RADIATION EFFECTS

CARLOS JULIO GONZALEZ AGUILERA

EVALUATION OF FAULT ATTACK DETECTION ON SRAM-BASED FPGAS

FABIO BENEVENUTI

EVALUATION OF MULTICORE SYSTEMS SOFT ERROR RELIABILITY USING VIRTUAL PLATFORMS

FELIPE ROCHA DA ROSA

EXPLOITING ABSOLUTE ARITHMETIC FOR POWER-EFFICIENT SUM OF ABSOLUTE DIFFERENCES

BRUNNO ALVES DE ABREU

FABRICATION AND CHARACTERIZATION OF A PH SENSOR

FRANCIO SOUZA BERTI RODRIGUES

FABRICATION AND OPTIMIZATION OF A PH SENSOR

FRANCIO SOUZA BERTI RODRIGUES

FAST-EXTRACT WITH CUBE HASHING

BRUNO DE OLIVEIRA SCHMITT

FAULT INJECTION METHODOLOGY FOR SINGLE EVENT EFFECTS ON CLOCK-GATED ASICS

LUIS ALBERTO CONTRERAS BENITES

FRAMEWORK-BASED ARITHMETIC CORE GENERATION TO EXPLORE ASIC-BASED PARALLEL BINARY MULTIPLIERS

LEANDRO MATEUS GIACOMINI ROCHA

IC BRAZIL PROGRAM TRAINING CENTERS: 8 YEARS EMPOWERING LATIN AMERICAN ENGINEERS TO WORK WITH MICROELECTRONICS

PEDRO FILIPE LEITE CORREIA DE TOLEDO

IMPACT OF SCHMITT TRIGGER INVERTERS ON PROCESS VARIABILITY ROBUSTNESS OF 1-BIT FULL ADDERS

SAMUEL PRESA TOLEDO

IMPACT OF SRAM IP ASPECT RATIO IN ASIC-ORIENTED VITERBI DECODER PHYSICAL IMPLEMENTATION

LEANDRO MATEUS GIACOMINI ROCHA

IMPLICATIONS OF WORK-FUNCTION FLUCTUATION ON RADIATION ROBUSTNESS OF FINFET XOR CIRCUITS

YGOR QUADROS DE AGUIAR

IMPROVED GOLDSCHMIDT ALGORITHM FOR FAST AND ENERGY-EFFICIENT FIXED-POINT DIVIDER

GUILHERME PEREIRA PAIM

INCORPORATION AND STABILITY OF PHOSPHORUS AT THE SIO2/SIC INTERFACIAL REGION DEPOSITED BY SPUTTERING

EDUARDO PITTHAN FILHO

INVESTIGATING PARALLEL TMR APPROACHES AND THREAD DISPOSABILITY IN LINUX

GENNARO SEVERINO RODRIGUES

LOW COST AUTOMATIC TEST VECTOR GENERATION FOR STRUCTURAL ANALOG TESTING

ANDRE LUCAS CHINAZZO

LOW POWER IEEE 802.11AH RECEIVER SYSTEM-LEVEL DESIGN AIMING FOR IOT APPLICATIONS

NELSON JUNQUEIRA DE ANDRADE

METAL-INSULATOR-SEMICONDUCTOR DIODE USING ALUMINUM, TITANIUM DIOXIDE AND SILICON.

RICARDO AUGUSTO ZANOTTO RAZERA

MONOCULAR VISUAL ODOMETRY WITH CYCLIC ESTIMATION

FABIO IRIGON PEREIRA

MRAM CONTROL TRANSISTOR RESILIENCE AGAINST HEAVY-ION IMPACTS

WALTER ENRIQUE CALIENES BARTRA

NI/AL2O3/4H-SIC SCHOTTKY DIODES

IVAN RODRIGO KAUFMANN

NI/AL2O3/4H-SIC SCHOTTKY DIODES FOR ALPHA PARTICLE DETECTOR

IVAN RODRIGO KAUFMANN

PASSIVATION ANALYSIS OF THE EMITTER AND SELECTIVE BACK SURFACE FIELD OF SILICON SOLAR CELLS

RICARDO AUGUSTO ZANOTTO RAZERA

POWER, PERFORMANCE AND ROBUSTNESS OF RADIATION HARDENED LATCHES UNDER VOLTAGE VARIABILITY

LEONARDO BARLETTE DE MORAES

PROCESS AND TEMPERATURE IMPACT ON SINGLE-EVENT TRANSIENTS IN 28NM FDSOI CMOS

WALTER ENRIQUE CALIENES BARTRA

PROJETO DE PORTAS LÓGICAS XOR COM REDUÇÃO DE POTÊNCIA POR VOLTAGE SCALING,

LEONARDO HEITICH BRENDLER

PRUNING AND APPROXIMATION OF COEFFICIENTS FORPOWER-EFFICIENT 2-D DISCRETE TCHEBICHEF TRANSFORM

GUILHERME PEREIRA PAIM

RADIATION SENSITIVITY OF XOR TOPOLOGIES IN MULTIGATE TECHNOLOGIES UNDER VOLTAGE VARIABILITY

YGOR QUADROS DE AGUIAR

ROBUSTNESS OF SUB-22NM MULTIGATE DEVICES AGAINST PHYSICAL VARIABILITY

ALEXANDRA LACKMANN ZIMPECK

ROUTABILITY DRIVEN FPGA PLACEMENT ALGORITHM FOR HETEROGENEOUS FPGAS

JULIA CASARIN PUGET

RSYN ? A PHYSICAL SYNTHESIS FRAMEWORK FOR RESEARCH AND EDUCATION

GUILHERME AUGUSTO FLACH

RUTHERFORD BACKSCATTERING SPECTROMETRY AS A VALUABLE TOOL TO CHARACTERIZE HFO2 FILMS GROWN BY ATOMIC LAYER DEPOSITION

SILMA ALBERTON CORREA

SELF-ALIGNED ZNO NANOPARTICLE-BASED TFTS FOR FLEXIBLE ELECTRONICS

FABIO FEDRIZZI VIDOR

SET RESPONSE OF FINFET-BASED MAJORITY VOTER CIRCUITS UNDER WORK-FUNCTION FLUCTUATION

YGOR QUADROS DE AGUIAR

SEU SUSCEPTIBILITY ANALYSIS OF A FEEDFORWARD NEURAL NETWORK IMPLEMENTED IN A SRAM-BASED FPGA

ISRAEL DA COSTA LOPES

TEMPERATURE DEPENDENCE AND ZTC BIAS POINT EVALUATION OF SUB 20NM BULK MULTIGATE DEVICES

YGOR QUADROS DE AGUIAR

UFRGSPLACE: ROUTABILITY DRIVEN FPGA PLACEMENT ALGORITHM FOR HETEROGENEOUS FPGAS

JULIA CASARIN PUGET

UNRAVELING THE OXIDATION MECHANISMS TAKING PLACE IN EARLY STEPS OF 4H-SIC DRY THERMAL OXIDATION

GUSTAVO HENRIQUE STEDILE DARTORA

USING ADDER AND SUBTRACTOR COMPRESSORS TO SUM OF ABSOLUTE TRANSFORMED DIFFERENCES ARCHITECTURE FOR LOW-POWER VIDEO ENCODING

BIANCA SANTOS DA CUNHA DA SILVEIRA

USING EFFICIENT ADDER COMPRESSORS WITH A SPLIT-RADIX BUTTERFLY HARDWARE ARCHITECTURE FOR LOW-POWER IOT SMART SENSORS

GUSTAVO MADEIRA SANTANA

VERY THIN SIO2 FILMS THERMALLY GROWN ON SIC: UNRAVELING THE MECHANISMS TAKING PLACE IN EARLY STEPS USING NUCLEAR REACTION

GUSTAVO HENRIQUE STEDILE DARTORA