{"id":187,"date":"2021-11-20T14:02:10","date_gmt":"2021-11-20T17:02:10","guid":{"rendered":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/?page_id=187"},"modified":"2022-08-24T10:52:18","modified_gmt":"2022-08-24T13:52:18","slug":"sforum-program","status":"publish","type":"page","link":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/sforum-program\/","title":{"rendered":"SForum Program"},"content":{"rendered":"\n

August 23th<\/strong><\/h1>\n\n\n
11:00 – 12:20 – KEYNOTE – Green Technologies for Intelligent and Connected Circuits & Systems Powered by Renewable Energy Sources<\/strong>
Massimo Alioto (NUS, Singapore)<\/strong>
Location: SBCCI Synopsys Auditorium<\/em>
Chair: Nuno Roma (IST, Portugal)<\/em><\/span><\/summary>
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ABSTRACT: The growth in the number of connected devices towards the trillion scale will be fundamentally impeded by batteries as a conventional source of energy, as their deployment in the trillions poses clear economic, logistical and environmental sustainability challenges.
This keynote introduces the key ideas and their silicon demonstrations to enable a new breed of always-on silicon systems from sensing, to computing and wireless communications with no battery inside (or any other energy storage). Sensor interfaces, processors and wireless transceivers fitting existing infrastructure (e.g., WiFi) with power reductions by orders of magnitude are discussed and exemplified by recent silicon demonstrations, and their system integration.
Ultimately, the technological pathway discussed in this keynote supports sustainable growth of applications leveraging large-scale deployments of silicon systems, making our planet smarter. And greener too.<\/p>\n\n\n\n

BIO: Massimo Alioto (Fellow, IEEE) is currently a Professor with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he leads the Green IC Group, and also the Director of the Integrated Circuits and Embedded Systems Area and the FD-FAbrICS research center on intelligent&connected systems. Previously, he held positions at the University of Siena (Italy), Intel Labs (USA), University of Michigan, Ann Arbor (USA), University of California at Berkeley (USA), and EPFL (Switzerland).
He has authored or coauthored about 350 publications on journals and conference proceedings. He is the coauthor of five books printed by Springer, including the popular Enabling the Internet of Things\u2014From Circuits to Systems (Springer, 2017). His research interests include self-powered integrated systems, intelligent and connected systems, widely energy-scalable integrated systems, data-driven systems for edge computing, hardware security, and emerging technologies.
Prof. Alioto is the Editor-in-Chief of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and is\/was a Distinguished Lecturer of the IEEE Solid-State Circuits and Circuits and Systems Society, for which he was also a member of the Board of Governors. He is\/was the Technical Program Chair (e.g., ISCAS 2023, SOCC, ICECS, and NEWCAS) in numerous conferences, and is in the IEEE \u201cDigital Architectures and Systems\u201d ISSCC Subcommittee and the IEEE ASSCC TPC. He has served as a Guest Editor for several IEEE journal special issues (e.g., JSSC, TCAS-I, TCAS-II, JETCAS) and an Associate Editor for a number of IEEE and ACM journals. He was the Deputy Editor-in-Chief of IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto is an IEEE Fellow.<\/p>\n\n\n\n

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18:00 – 19:00 – PANEL – Forma\u00e7\u00e3o de Talentos<\/strong> (in portuguese)
Location: Panels ABISEMI Room<\/em><\/span><\/summary>
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Painel 1: Desenvolvimento de Talentos para a Ind\u00fastria de Semicondutores
Organizador\/Moderador: Marcelo Lubaszewski, UFRGS
Painelistas:
Linnyer Beatrys Ruiz Aylon, Projeto Mann\u00e1 – UEM
Alcides S. Costa, InPlace Design Automation
Rodrigo Alves de Lima Moreto, MTG2i Solutions Ltda<\/p>\n\n\n\n

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August 24th<\/strong><\/h1>\n\n\n
11:00 – 12:20 – KEYNOTE – Reliability of VLSI technologies: impediment and opportunity<\/strong>
Ben Kaczer (IMEC, Belgium)<\/strong>
Location: SBMicro Cadence Auditorium<\/em>
Chair: Gilson Wirth (UFRGS, Brazil)<\/em><\/span><\/summary>
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ABSTRACT: Presence of non-idealities and defects in VLSI technologies is an immutable reality, which, however, is often overlooked by device engineers, researchers, technologists, and designers alike. We argue that in fact VLSI reliability \u201cmakes or breaks\u201d any new technology. Superficial device reliability optimization is possible using phenomenological observations only, but we argue that solid physical foundations and thorough understanding of the underlying degradation mechanisms are essential both for truly dependable lifetime projections and for novel device pathfinding. Based on the detailed investigation of gate oxide defects, our \u201cdefect engineering\u201d approach enables, among other things, optimization paths for SiGe channel devices and new oxidation techniques for advanced gate-all-around architectures, such as nanosheets and forksheets. In deeply scaled devices, degradation mechanisms can be decomposed down to individual defects, with each defect measured separately and its properties described down to single Kelvin temperatures using quantum mechanics. Such knowledge then allows us e.g. to model the degradation statistics of deeply-scaled devices and to predict the likelihoods of their failure. Robust degradation models enable us to project wider safe operating areas, which in turn allow to design better-performing circuitry at a given technology node and thus limited costs. Moreover, the ubiquitous presence of defects can be in fact embraced and the in-depth knowledge of defect properties can be used to our advantage to design new devices and applications, ranging from memory to physically unclonable functions and tamper-aware aging monitors.<\/p>\n\n\n\n

BIO: Dr. Ben Kaczer is a Scientific Director in the FEOL reliability group at imec. Dr. Kaczer received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively. For his Ph.D. research on the ballistic-electron emission microscopy of SiO2 and SiC films he received the OSU Presidential Fellowship and support from Texas Instruments, Inc. In 1998 he joined the reliability group of imec, Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple-gate FETs, circuits, and characterization of Ge, SiGe, III-V, and MIM devices.
He has co-authored more than 500 journal and conference papers and 4 patent groups related to device and circuit reliability, presented a number of invited papers and tutorials, and received 6 IEEE International Reliability Physics Symposium (IRPS) Best and Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. In 2019 he was historically the most cited author of IRPS. His h-index on Google Scholar is 62.
Dr. Kaczer has served twice as the chair of the Characterization, Reliability and Yield subcommittee of the International Electron Device Meeting (IEDM; 2007 and 2015) and as a member of various subcommittees of the IRPS (2002\u20142016) and is currently serving as a member of IRPS management committee (2018\u2014). He was the General Chair of the Semiconductor Interfaces Specialists Conference (SISC; 2006) and continues to act as the conference secretary (2007\u2014). He co-organized the INFOS conference (2005), and served on the INFOS, WoDiM, IPFA, and ICICDT conference committees. He has served on the Editorial Board of IEEE journal of Transaction of Electron Devices for three terms (2011\u20142019).<\/p>\n\n\n\n

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18:00 – 19:00 – PANEL – International Industry <\/strong>(in english)
Location: Panels ABISEMI Room<\/em><\/span><\/summary>
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The Brazilian Semiconductor Industry: New Opportunities?
Organizer: Marcelo Lubaszewski, UFRGS
Moderator: Arthur Liraneto, CESAR
Panelists:
Murilo Pessatti, Chipus Microelectronics
Julio Le\u00e3o da Silva Jr., Ensilica
J\u00falio de Oliveira, Idea! Electronic Systems<\/p>\n\n\n\n

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 August 25th<\/strong><\/h1>\n\n\n\n

Devices <\/strong><\/strong><\/span>
Location: SForum Smart Room
Chair: Paula Agopian (UNESP)<\/span><\/em><\/p>\n\n\n\n

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09:20 \u2014 09:40<\/span><\/td>Evaluation of Analog Parameters in SOI Nanowires nMOSFETs<\/span>
Vin\u00edcius Rodrigues Prates, Michelly de Souza<\/em><\/td><\/tr>
09:40 \u2014 10:00 <\/span><\/td>Effect of Channel Width Variability on the Electrical Characteristics of SOI Triple Gate Junctionless Transistors<\/span>
Victor Nogueira Cirillo, Rodrigo Doria<\/em><\/td><\/tr>
10:00 \u2014 10:20<\/span><\/td>On the implementation of a position-dependent charge carrier mass in NEGF simulations<\/span>
F\u00e1bio da Silva Le\u00e3o, Diego Neves de Lemos, Stefan Blawid<\/em><\/td><\/tr>
10:20 \u2014 10:40<\/span><\/td>A Temperature Compensation Circuit Based on Bandgap Reference<\/span>
Josu\u00e9 Marinho Costa, Wilmar Bueno de Moraes, Jair Lins de Emeri Jr., Antonio Telles, Saulo Finco, Luis Eduardo Seixas<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n
11:00 – 12:20 – KEYNOTE – State of Video Codecs: AV1 and VVC algorithms and deployment<\/strong>
Iole Moccagatta (INTEL, USA)<\/strong>
Location: SBCCI Synopsys Auditorium<\/em>
Chair: Bruno Zatt (UFPel, Brazil)<\/em><\/span><\/summary>
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ABSTRACT: TBD<\/p>\n\n\n\n

BIO: Dr. Iole Moccagatta is a Principal Engineer at Intel working on HW Multimedia IPs that are integrated on Intel platforms. Prior to Intel she hold the position of Senior Video Architect at NVIDIA, and that of Science Director at IMEC, Belgium. Dr. Moccagatta has been a very active member of MPEG, ITU-T, and JPEG, where she has represented US interests and companies and made a large number of technical contributions. A number of those have been included in MPEG and JPEG standards. She is currently Co-chair of the MPEG\/ITU-T Joint Video Experts Team (JVET) Ad-Hoc Group on H.266\/VVC Conformance and Co-editor of the H.266\/VVC Conformance Testing document. Dr. Moccagatta has also been an active participant of the Alliance for Open Media (AOM) AV1 Codec WG, where she has co-authored two adopted proposals. She currently represents Intel in the AOM Board. Dr. Moccagatta is also serving as IEEE Signal Processing Society (SPS) Regional Director-at-Large Regions 1-6, supporting and advising Chapters and their officers, providing input on how to serve and engage the SPS community in general, and the SPS industry members in particular, and using her professional network to attract new volunteers to serve in SPS subcommittees and task forces. Dr. Moccagatta is the author or co-author of more than 30 publications, 2 book chapters, and more than 10 talks and tutorials in the field of image and video coding. She holds more than 10 patents in the same fields. For more details see Dr. Moccagatta professional site at http:\/\/alfiole.users.sonic.net\/iole\/. Dr. Moccagatta received a Diploma of Electronic Engineering from the University of Pavia, Italy, and a PhD from the Swiss Federal Institute of Technology in Lausanne, Switzerland.<\/p>\n\n\n\n

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Analog & RF Design I<\/strong><\/strong><\/span>
Location: SForum Smart Room
Chair: Alessandro Girardi (Unipampa)<\/span><\/em><\/p>\n\n\n\n

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14:40 \u2014 15:00 <\/span><\/td>Behavioral Models of Power Amplifier Using Multiple One-Dimensional Polynomial Functions and Multiple Finite Impulse Response Filters<\/span>
Lara Eimy Kuada, Eduardo Gon\u00e7alves de Lima<\/em><\/td><\/tr>
15:00 \u2014 15:20<\/span><\/td>Loadpull simulations of a CMOS stacked power amplifier with 16QAM IEEE 802.11ax signals<\/span>
Enzo Bonametti Coutinho, Bernardo Leite, Favero Santos<\/em><\/td><\/tr>
15:20 \u2014 15:40 <\/span><\/td>Design of a Digital CIC Filter for an Audio Sigma-Delta ADC in the Scilab Environment
Otavio Elias Viana de Freitas, Edivania Edivania Ferreira Silva, Cristian M\u00fcller, Paulo C\u00e9sar Comassetto de Aguirre<\/em><\/td><\/tr>
15:40 \u2014 16:00<\/span><\/td>Stability and Linearity Improvement in a Multi-Mode CMOS Power Amplifier<\/span>
Matheus S. Quadros, Bruno Tarui, Bernardo Leite<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Analog & RF Design II<\/strong><\/strong><\/span>
Location: SForum Smart Room
Chair: Paulo C\u00e9sar Aguirre (Unipampa)<\/span><\/em><\/p>\n\n\n\n

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16:20 \u2014 16:40 <\/span><\/td>Quasi-Periodic Steady-State and Periodic AC Applied for One Large and One Small Signal Tone<\/span>
Jos\u00e9 Eduardo da Silva, Eduardo Lima<\/em><\/td><\/tr>
16:40 \u2014 17:00<\/span><\/td>Linearization of Circuits with Polynomial Nonlinearities Described in the Frequency Domain<\/span>
Leticia Cordeiro, Eduardo Gon\u00e7alves Lima<\/em><\/td><\/tr>
17:00 \u2014 17:20 <\/span><\/td>Real-valued Neural Network Based in Group Method of Data Handling Applied to Power Amplifier Modeling
Ana Paula Princival Machado, Eduardo Lima<\/em><\/td><\/tr>
17:20 \u2014 17:40<\/span><\/td>Parameter Identification of a Power Amplifier Behavioral Model Using a Derivative-free Damping Switchable Levenberg-Marquardt Method
Felipe P. Ribeiro, Eduardo Lima<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
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18:00 – 19:00 – PANEL – PDI Microeletr\u00f4nica<\/strong> (in portuguese)
Location: Panels ABISEMI Room<\/em><\/span><\/summary>
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Forma\u00e7\u00e3o de RH e Projetos de PD&I no Brasil: Perspectivas para a Microeletr\u00f4nica
Organizador: Marcelo Lubaszewski, UFRGS
Moderadora: Linnyer Beatrys Ruiz Aylon, SBMicro
Painelistas:
Alexandre Motta, COAPD – CNPq
Valeria Arruda, Engenharias IV – CAPES
Carlos Eduardo Pereira, Embrapii<\/p>\n\n\n\n

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 August 26th<\/strong><\/h1>\n\n\n\n

Applications<\/strong><\/strong><\/span>
Location: SForum Smart Room
Chair: Daniel Palomino (UFPel)<\/span><\/em><\/p>\n\n\n\n

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09:20 \u2014 09:40<\/span><\/td>Approximated Ripple Carry Adders Evaluation<\/span>
Andrei Pochmann Koenich, Gabriel Ammes, Paulo Butzen, Renato Ribas<\/em><\/td><\/tr>
09:40 \u2014 10:00 <\/span><\/td>Hardware Design for the Interpolation Filters of the VVC Standard Affine Motion Estimation<\/span>
Denis Maass, Murilo Perleberg, Vladimir Afonso, Luciano Agostini, Marcelo Porto<\/em><\/td><\/tr>
10:00 \u2014 10:20<\/span><\/td>Assessment of Different Coding Units Usage in VVC Inter-Frame Prediction<\/span>
Ramiro Gomes da Silva Viana, Fernando Sagrilo, Marta Loose, Gustavo Sanchez, Guilherme Corr\u00eaa, Luciano Agostini<\/em><\/td><\/tr>
10:20 \u2014 10:40<\/span><\/td>Identifying Energy-Saving Opportunities for AV1 Video Coding in Streaming Services<\/span>
Caroline Souza Camargo, Alex Borges, Guilherme Corr\u00eaa<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
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11:00 – 12:20 – KEYNOTE – Towards Next Generation Logic Synthesis and Verification<\/strong>
Alan Mishchenko (University of California, Berkeley, USA)<\/strong><\/strong>
Location: SBMicro Cadence Auditorium<\/em>
<\/strong>Chair: Andr\u00e9 Reis (UFRGS, Brazil)<\/em><\/span><\/summary>
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ABSTRACT: Given the progress achieved over the last fifty years in logic synthesis and verification, it is tempting to believe that most of the research discoveries have already been made, and the role of future researchers and engineers is just to maintain the CAD tools and occasionally make small changes, such as adding concurrency or employing machine learning to generate better scripts. Nothing could be farther from the truth. In this talk, we explore several orthogonal innovations in the fundamental research used to build synthesis tools targeting FPGAs and ASICs. These innovations include using novel data structures, leveraging synergistic optimization engines, and simultaneously exploring previously-unrelated search spaces. Most of these improvements are work-in-progress with early results demonstrating better quality and faster runtimes.<\/p>\n\n\n\n

BIO: Alan graduated with M.S. from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and received his Ph.D. from Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. In 2002, Alan joined the EECS Department at University of California, Berkeley, where he is currently a full researcher. His research is in computationally efficient logic synthesis, formal verification, and machine learning.<\/p>\n\n\n\n

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CAD<\/strong><\/span>
Location: SForum Smart Room
Chair: Cl\u00e1udio Diniz (UFRGS)<\/span><\/em><\/p>\n\n\n\n

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14:40 \u2014 15:00 <\/span><\/td>Synthesis of an Amber 23 Open-Core Processor
Leonardo Reinehr Gobatto, J\u00falia Dartora Craide, Jonas Fogliarini Gava, Vitor Bandeira, Ricardo Reis<\/em><\/td><\/tr>
15:00 \u2014 15:20<\/span><\/td>Exploring Curriculum Learning on a CGP Logic Optimization Flow<\/span>
Naiara Sachetti, Bryan Martins Lima, Augusto Berndt, Cristina Meinhardt, Jonata T. Carvalho<\/em><\/td><\/tr>
15:20 \u2014 15:40 <\/span><\/td>Design and Transistor-Level Simulation of a High-Order Gm-C Filter Bank<\/span>
Maria J\u00falia Prata e Cunha, Ant\u00f4nio Borges Moreira, Mateus Xavier Ferreira, Est\u00eav\u00e3o Coelho Teixeira<\/em><\/td><\/tr>
15:40 \u2014 16:00<\/span><\/td>Rushing the CGP Logic Optimization Flow<\/span>
Bryan Martins Lima, Naiara Sachetti, AUGUSTO BERNDT, Cristina Meinhardt, J\u00f4nata Tyska Carvalho<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Best Papers<\/strong><\/strong><\/span>
Location: SForum Smart Room
Chair: Guilherme Corr\u00eaa (UFPel)<\/span><\/em><\/p>\n\n\n\n

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16:20 \u2014 16:40 <\/span><\/td>A Low-Power 0.4-V Negative Resistance-Based Small-Signal Amplifier<\/span>
Suzian M. Santos, Madaglena Mbuy Mikue, Lucas Compassi Severo<\/em><\/td><\/tr>
16:40 \u2014 17:00<\/span><\/td>Design and Characterization of a 0.9-V Differential Inverter-Based OTA<\/span>
BEATRIZ ESTEFANIA HATSCHBACH REZENDE, Matheus Cortez, Alessandro Girardi, Paulo C\u00e9sar Comassetto de Aguirre<\/em><\/td><\/tr>
17:00 \u2014 17:20 <\/span><\/td>Convolutional Neural Network to recognize 2-Input Gates for Silicon Quantum Dot<\/span>
Emanuel Vitor Ruella, Maria Dalila Vieira, Omar P. V. Neto<\/em>, Ricardo Ferreira, Jos\u00e9 Augusto Nacif<\/em><\/td><\/tr>
17:20 \u2014 17:40<\/span><\/td>Design and Characterization of a Dynamic Bias Latch-type CMOS Comparator<\/span>
Jo\u00e3o Lucas Johan Brum, Matheus Cortez, Martina Correa Rodrigues, Alessandro Girardi, Paulo C\u00e9sar Comassetto de Aguirre<\/em><\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Times are expressed in GMT-3<\/strong><\/p>\n","protected":false},"excerpt":{"rendered":"

August 23th August 24th  August 25th Devices Location: SForum Smart RoomChair: Paula Agopian (UNESP) 09:20 \u2014 09:40 Evaluation of Analog Parameters in SOI Nanowires nMOSFETsVin\u00edcius Rodrigues Prates, Michelly de Souza 09:40 \u2014 10:00 Effect...<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-187","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/pages\/187","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/comments?post=187"}],"version-history":[{"count":22,"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/pages\/187\/revisions"}],"predecessor-version":[{"id":1517,"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/pages\/187\/revisions\/1517"}],"wp:attachment":[{"href":"https:\/\/www.ufrgs.br\/chip-in-the-minuano\/wp-json\/wp\/v2\/media?parent=187"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}