{"id":1899,"date":"2021-04-21T22:11:19","date_gmt":"2021-04-21T22:11:19","guid":{"rendered":"https:\/\/www.ufrgs.br\/emicro\/?page_id=1899"},"modified":"2021-04-26T16:35:04","modified_gmt":"2021-04-26T16:35:04","slug":"sim","status":"publish","type":"page","link":"https:\/\/www.ufrgs.br\/emicro\/sim\/","title":{"rendered":"Papers SIM 2021\u200b"},"content":{"rendered":"\t\t
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Papers SIM 2021<\/h1>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t
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SIM 1: AV1 Hardware Design
Segunda, 26 de abril, das 10:00 \u00e0s 10:50<\/h2>\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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Hardware Design of Directional Intra-Prediction Decoder for the AV1 Codec<\/b>
Jones Goebel, Luciano Agostini, Bruno Zatt and Marcelo Porto<\/p>

VLSI implementation of the Smooth Interpolation Filter for AV1 codecs<\/b>
Bruna Suemi Nagai, Daiane Freitas, Guilherme Corr\u00eaa and Mateus Grellert<\/p>

A Hardware Architecture for the AV1 Intra Frame Prediction Using Operation Sharing
<\/b>Luiz Neto, Marcel Moscarelli Corr\u00eaa, Daniel Palomino, Luciano Agostini and Guilherme Corr\u00eaa<\/span><\/p>

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation
<\/b>William Kolodziejski, Robson Domanski, Marcelo Porto, Bruno Zatt and Luciano Agostini<\/p>

Deblocking Filter Architecture for UHD AV1 Decoder Targeting UHD Videos<\/b>
Eduardo Zummach, Roberta Palau, Jones Goebel, Guilherme Correa, Luciano Agostini and Marcelo Porto<\/p>

AE-AV1: a pipelined architecture for the AV1 arithmetic encoder
<\/b>Tulio Pereira Bitencourt, F\u00e1bio Ramos and Sergio Bampi<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 2: <\/span>Approximate Design and Tools
Segunda, 26 de abril, das 11:00 \u00e0s 11:50<\/span>
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Two-Level Approximate Logic Synthesis
<\/b>Gabriel Ammes, Walter Lau Neto, Paulo Butzen, Pierre-Emmanuel Gaillardon and Renato Ribas<\/p>

Combining Refactoring and Approximated-Adders to Design Energy-efficient Gaussian Filters
<\/b>Marcio Monteiro, Pedro Aquino, Ismael Seidel, Mateus Grellert, Leonardo Soares, Jose Luis G\u00fcntzel and Cristina Meinhardt<\/p>

An Automatic Flow for Precise and Approximated Synthesis
<\/b>Isac Campos, Augusto Berndt, Brunno de Abreu, J\u00f4nata Carvalho, Mateus Grellert and Cristina Meinhardt<\/p>

Exploring 4-bit Approximated Comparators on a Decision Tree Classification Model
<\/b>Pedro Aquino Silva, Mateus Grellert and Cristina Meinhardt<\/p>

An Approximate Functions Generation Method to ATMR Architecture
<\/b>Guilherme Barbosa Manske, Leomar Soares da Rosa Junior and Paulo Francisco Butzen<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 3: <\/span>Analog Design and Backend I
Ter\u00e7a, 27 de abril, das 09:00 \u00e0s 09:50<\/span>
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Modified Polar Volterra series with thirty-two independent truncations applied in modeling of competing dual-band power amplifiers
<\/b>Bianca Oliveira, Luis Schuartz and Eduardo Lima<\/p>

Modelling the Equivalent Output Resistance of Integrated SC DC-DC Converters Including Source Resistance Effects
<\/b>Luis Felipe Machado Dutra, Alessandro Gon\u00e7alves Girardi and Lucas Compassi-Severo<\/p>

Analysis and Optimization of Fine-Pitch Gold Wire Ball Bonding Thermosonic Parameters
<\/b>Arthur L. Bohn, Cassiano S. de Campes, Sandro J. Rigo and Rodrigo M. de Figueiredo<\/p>

Simulation of a multimode CMOS power amplifier with LTE signals<\/b>
Enzo Coutinho, Bruno Tarui and Bernardo Leite<\/p>

A 0.6-V Rail-to-Rail Input 3-Bit Flash ADC in 180-nm
<\/b>Ramon H. Vieira, Edivania F. Silva and Paulo C. C. de Aguirre<\/p>

A Versatile Discrete-Time Wake-up Receiver for LoRaWAN applications
<\/b>Fernando Ferreira, Pietro Ferreira and Sandro Ferreira<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 4: <\/span>Analog Design and Backend II
Ter\u00e7a, 27 de abril, das 10:00 \u00e0s 10:50<\/span>
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Analysis of the Quantization Noise Impact on a QAM demodulator using a Python Toolbox<\/b>
Arthur C. Morbach, Jonas D. de Castro and Sandro B. Ferreira<\/p>

Design of an Information-Set Decoder in CMOS 130 nm
<\/b>Jefferson Rodrigo Schuertz, Carlos Alexandre Gouvea da Silva and Sibilla Batista da Luz Fran\u00e7a<\/p>

IR-UWB Pulse Synthesizer Based on a Sample & Hold Envelope Shaping Circuit
<\/b>Felipe Schoulten, Andr\u00e9 Mariano, R\u00e9my Vauche, Sylvain Bourdel, Jean Gaubert, Nicolas Dehaese and Herv\u00e9 Barthelemy<\/p>

A Single-Stage Rail-to-Rail OTA for sub-0.5V Applications
<\/b>Martina Rodrigues and Paulo Aguirre<\/p>

Design of a 1-bit Analog-to-Digital Converter in CMOS Technology Dedicated to 5G Communication Systems
<\/b>Alexandre Z. Morais and Andre Mariano<\/span><\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 5: <\/span>Arithmetic\/Processor Circuits Design and Tools
Quarta, 28 de abril, das 09:00 \u00e0s 09:50<\/span>
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Improving the Design of FFT Architectures Using Multiple Constant Multiplication<\/b>
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Sidinei Ghissoni and Eduardo Costa<\/p>\n

Evaluation of Variability Aspects in a FinFET NAND-Based Full-Adder
<\/b>Gerson Andrade, Eduardo Costa and Alexandra Zimpeck<\/p>\n

A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization
<\/b>Leonardo Reinehr Gobatto, Mateus Saquetti Pereira de Carvalho Tirone, Raphael Martins Brum, Bruno Zatt, Samuel Nascimento Pagliarini, Weverton Luis da Costa Cordeiro and Jos\u00e9 Rodrigo Furlanetto Azambuja<\/p>\n

A Non-Volatile Processor Design Using Shadow Registers Based on STT-MTJs
<\/b>Bruna Cagliari, Paulo Butzen and Raphael Brum<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 6: <\/span>Energy Saving Design and Analysis
Quarta, 28 de abril, das 10:00 \u00e0s 10:50<\/span>
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An Energy-Efficient Wavelet Haar Transform Architecture for Respiratory Signal Processing
<\/b>Morgana Macedo Azevedo Da Rosa, Henrique Bestani Seidel, Guilherme Paim, Eduardo Da Costa, S\u00e9rgio Almeida and Sergio Bampi<\/p>

Alternative Approaches to Explore Energy-efficient Multipliers
<\/b>Vin\u00edcius Zanandrea, Douglas Borges, Vagner Rosa and Cristina Meinhardt<\/p>

A Low-impact overhead technique for configurable and energy-efficient 2D Gaussian Filter Design
<\/b>Talita Borges, Cristina Meinhardt and Leonardo Soares<\/p>

Energy consumption comparison on Crossbar Memories<\/b>
Bruno Soares Zimmer, Paulo Francisco Butzen and Raphael Martins Brum<\/p>

A Design Flow of Tree-Based Inference Engines for Low-Power Learning Applications
<\/b>Brunno Abreu, Mateus Grellert and Sergio Bampi<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 7: <\/span>Fault Tolerance and Test
Quinta, 29 de abril, das 09:00 \u00e0s 09:50<\/span>
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Majority Voters Fault Tolerance Evaluation
<\/b>Ingrid Oliveira, Rafael Schvittz, Leomar Rosa Jr, Rafael Soares and Paulo F. Butzen<\/p>\n

A Tool Based on the Monte Carlo Method to Assess Fault Masking in Digital Circuits
<\/b>Clayton Farias, Paulo Butzen, Rafael Schvittz and Vagner Rosa<\/p>\n

Exploitation of Fault Tolerance Techniques in Multicores APSoCs
<\/b>Newton Lacerda, D\u00e9bora Matos and Fernanda Kastensmidt<\/p>\n

Gate Mapping and Voltage Influence on Radiation Robustness: a C17 Benchmark Case-Study
<\/b>Bernardo Borges Sandoval, Leonardo Heitich Blender, Alexandra L. Zimpeck, Fernanda L. Kastensmidt, Ricardo Reis and Cristina Meinhardt<\/p>\n

<\/p>\n

Robustness Evaluation of DICE SRAM at the limits of bulk CMOS and FinFET technologies
<\/b>Cleiton M. Marques, Maria Eduarda de Melo Hang, Leonardo H. Brendler, Alexandra L. Zimpeck, Ricardo Reis, Cristina Meinhardt and Paulo F. Butzen<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 8: <\/span>AI and Statistics
Quinta, 29 de abril, das 10:00 \u00e0s 10:50<\/span>
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Electrical Behavior Prediction Of An Inverter Using Machine Learning Algorithms
<\/b>Gabriel Lima Jacinto and Cristina Meinhardt<\/p>

A Study on State-of-the-Art Techniques for Recognizing Vehicle Plates in Real-Time
<\/b>George de Borba Nardes and Cesar Albenes Zeferino<\/p>

Exploring Perceptron Architectures for Power-Efficient Neural Networks<\/b>
Luis Antonio Simon, Brunno Abreu and Mateus Grellert<\/p>

Stroke Detection Separation Algorithm for Storm Detector Network (SDN)<\/b>
Augusto Mathias Adams, Armando Heilmann and C\u00e9sar Augusto Dartora<\/p>

Quality and Complexity Evaluation of Learning-Based Image Compression Techniques<\/b>
Joao Dick, Brunno Abreu, Mateus Grellert and Sergio Bampi<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t

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SIM 9: <\/span>EDA
Sexta, 30 de abril, das 09:00 \u00e0s 09:50<\/span>
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A Placement-Based Predictor For DRVs Considering Advanced Routing Constraints<\/b>
Sheiny Almeida, Aysa Tabrizi, Erfan Aghaeekiasaraee, Renan Netto, Tiago Fontana, Upma Gandhi, La\u00e9rcio Pilla, Jos\u00e9 Lu\u0131\u0301s G\u00fcntzel, Laleh Behjat and Cristina Meinhardt<\/p>\n

Limitations on Using Fixed Gate Reliability Values for Realistic Reliability Circuit Estimation
<\/b>Matheus Pontes, Rafael Schvittz, Leomar Rosa Jr and Paulo F. Butzen<\/p>\n

Bootstrapping Logic Optimization Techniques With Cartesian Genetic Programming
<\/b>Augusto Berndt, Isac Campos, Brunno Abreu, Mateus Grellert, Jonata Carvalho and Cristina Meinhardt<\/p>\n

A Study on STT-MTJ Based Non-Volatile Flip-Flop Topologies
<\/b>Klaus Holler, Raphael M. Brum and Paulo F. Butzen<\/p>\n

CREsT – Circuit Reliability Estimation Tool
<\/b>Matheus Pontes, Gl\u00f3ria Claro, Clayton Farias, Marcio O. da Rocha, Rafael Schvittz, Leomar Rosa Jr and Paulo F. Butzen<\/p>

Automatic Cell Layout Generation – ALTRAN. Elias de Almeida Ramos<\/b>
Vitor Hugo F. Maciel, Germano Girondi and Ricardo Augusto da Luz Reis
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SIM 10: <\/span>Video Coding
Sexta, 30 de abril, das 10:00 \u00e0s 10:50<\/span>
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Complexity Reduction of H.266\/VVC Encoders Using Decision Trees
<\/b>Arthur Cerveira, Bruno Zatt, Luciano Agostini and Felipe Sampaio<\/p>

A CTU-based IME Approach for Multiple Block Sizes in a Redundancy-Free Hardware Design
<\/b>Murilo Perleberg, Vladimir Afonso, Bruno Zatt, Luciano Agostini and Marcelo Porto<\/p>

Evaluations of Video Decoding for EnablingProcessing-in-Memory Design
<\/b>Garrenlus Souza, Felipe Sampaio, Sergio Bampi and Bruno Zatt<\/p>

A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change
<\/b>Vinicius Borges, Murilo Perleberg, Vladimir Afonso, Marcelo Porto and Luciano Agostini<\/p>

Analysis of the Versatile Video Coding Standard Complexity and Compression Efficiency
<\/b>Icaro Siqueira, Guilherme Corr\u00eaa and Mateus Grellert<\/p><\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

Papers SIM 2021 SIM 1: AV1 Hardware DesignSegunda, 26 de abril, das 10:00 \u00e0s 10:50 Hardware Design of Directional Intra-Prediction Decoder for the AV1 CodecJones Goebel, Luciano Agostini, Bruno Zatt and Marcelo Porto VLSI implementation of the Smooth Interpolation Filter for AV1 codecsBruna Suemi Nagai, Daiane Freitas, Guilherme Corr\u00eaa and Mateus Grellert A Hardware Architecture …<\/p>\n

Papers SIM 2021\u200b<\/span> Read More »<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/pages\/1899"}],"collection":[{"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/comments?post=1899"}],"version-history":[{"count":35,"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/pages\/1899\/revisions"}],"predecessor-version":[{"id":2074,"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/pages\/1899\/revisions\/2074"}],"wp:attachment":[{"href":"https:\/\/www.ufrgs.br\/emicro\/wp-json\/wp\/v2\/media?parent=1899"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}