Paula Ghedini Der Agopian - Universidade Estadual de São Paulo (UNESP) - São João da Boa Vista, SP, Brazil
Technological Evolution Effects on the Basic Parameters of Advanced Transistors

Abstract:
The technological evolution experienced in the last decades has required an aggressive miniaturization of the devices and a huge evolution in the fabrication processes. As a result of each step of this evolution it is observed a change in the electrical behavior of the devices. In order to be able to design a new circuit or propose a new application it is essential that we are able to predict the operation of these new transistors. The effects caused by technological evolution on the basic parameters of transistors will be discussed for different transistor technologies, from the advent of SOI tecnology to devices that has being considered for sub 7nm technology node.

Short Bio:
Graduated in Electrical Engineering at FEI (2000), master's (2003) and PhD (2008) degrees in Electrical Engineering (microelectronics) at University of São Paulo. The postdoctoral was held at the Polytechnic School of the University of São Paulo in cooperation with the Imec / Belgium Research Center (2014). She managed the Integrated Circuit Training Center at USP Polytechnic School of the CI-Brazil program. She is currently a professor at São Paulo State University (UNESP) and a associate researcher at the University of São Paulo. Has experience in Electrical Engineering, focusing on microelectronics, acting on the following subjects: SOI CMOS Technology, FinFET, Radiation, Tensioned Devices, and Tunneling Transistors (TFETs). He is a senior member of IEEE and Vice President of the IEEE Electron Devices Society (EDS) Chapter of the South-Brazil Section. She is a CNPq Level 1D-productivity researcher and participates in international cooperation projects between Brazil and Belgium.

Mateus Grellert - Universidade Católica de Pelotas (UCPEL) - Pelotas, RS, Brazil
Deep Machine Learning - Current Status and Trends

Abstract:
In this talk, an overview of the current research in Machine Learning is initially given, defining the main topics that are being targeted by the academic community. Afterward, case studies from published works in the literature are discussed, including activities being developed at the Graduate Program in Electrical and Computing Engineering (PPGEEC-UCPel). The topics that are presented in detail include: Deep Learning, Machine Learning applied to Biomedical Science, and Circuits and Systems for Machine Learning algorithms. For each subject, the main challenges involved and the way researchers are addressing them are discussed.

Short Bio:
Prof. Mateus Grellert received the M.Sc. degree in Computer Science from the Federal University of Rio Grande do Sul (UFRGS), Brazil, in 2014, and the Ph.D. degree at the same University in 2018. He is an Assistant Professor at the Catholic University of Pelotas, Brazil. He is also a member of the Joint Group on Audio, Image, Multimedia and Hypermedia Coding (CE-021:000.029) from the Brazilian Association of Norms and Techniques (ABNT). He has been doing research in embedded systems solutions for more than 8 years. His published works include topics like reconfigurable architectures, memory-aware and energy-aware design, and efficient video-coding systems. His current research interests involve video-coding optimization, applied Machine Learning, circuits and systems for machine learning algorithms, and video-coding systems in constrained, embedded applications.

Marco Aurélio Wehrmeister - Universidade Tecnológica Federal do Paraná (UTFPR) - Curitiba, PR, Brazil
Applying Model-Driven Engineering in the Hw/Sw co-design of Real-Time Embedded Systems

Abstract:
This talk will present methods and techniques applied in the co-design of real-time embedded systems, specifically those that are implemented as a System-on-Chip (SoC) that includes components with reconfigurable logic (FPGA). The target application domain is automation systems domain. The main objective is to discuss techniques and methods that use high-level abstractions, such as UML/MARTE models and concepts of the Aspect-Oriented Software Development (AOSD), for an integrated co-design approach that addresses both software and hardware design. To this end, we will introduce model-driven engineering (MDE) techniques combined with separation of concerns in the handling of functional and non-functional requirements. Automatic transformations between models allow the information specified in different high-level modeling languages to be integrated and shared within the (co-)design of the hardware and software components. To illustrate such transformations, code generation techniques will be presented for software components (e.g., java and C / C++) and also to hardware (VHDL) applied in some case studies that represents real-world applications. Results indicate that the abstraction increase obtained by using MDE and the separation of concerns leads to an improvement in the reuse and adaptation of both software and hardware components.

Short Bio:
Marco Aurélio Wehrmeister received a Ph.D. degree in Computer Science from the Federal University of Rio Grande do Sul (Brazil) and the University of Paderborn (Germany) in 2009 (double-degree). In 2009, he worked as a Lecturer and Postdoctoral Researcher for the Federal University of Santa Catarina (Brazil). From 2010 to 2013, he worked as a tenure-track Professor with the Department of Computer Science from the Santa Catarina State University (UDESC, Brazil). Since 2013, he has been working as a tenure track Professor with the Department of Informatics from the Federal University of Technology - Paraná (UTFPR, Brazil). From 2014 to 2016, he was the Head of the M.Sc. course on Applied Computing of UTFPR. In 2015, Prof. Dr. Wehrmeister was a Visiting Fellow (short stay) with the School of Electronic, Electrical and Systems Engineering from the University of Birmingham (UK). Prof. Dr. Wehrmeister's thesis was selected by the Brazilian Computer Society as one of the six best theses on Computer Science in 2009. He is the current chair of the special commission on Computing Systems Engineering of the Brazilian Computer Society and also a member and vice-chair of the IFIP Working Group 10.2 on Embedded Systems. His research interests are in the areas of embedded and real-time systems, aerial robots, model-driven engineering, and hardware/software engineering for embedded real-time systems and robotics. Prof. Dr. Wehrmeister has co-authored more than 75 papers in international peer-reviewed journals and conference proceedings. He has been a reviewer for various international journals, as well as a member of the technical program committee of various conferences and symposiums. Prof. Dr. Wehrmeister was the general chair of the IFIP International Workshop on Software Technologies for Future Embedded and Ubiquitous Systems (SEUS 2014), the Brazilian Embedded Systems School (ESSE 2015), the Brazilian Symposium on Computing Systems Engineering (SBESC 2017), and the International Embedded Systems Symposium (IESS 2019). Besides, he was TPC chair of the Brazilian Symposium on Computing System Engineering (SBESC 2014), the IFIP International Embedded Systems Symposium (IESS 2015), and 19th IEEE International Symposium on Real-Time Computing (ISORC 2016). In 2018, he got a productivity research grant (in Portugues, Bolsa de Produtividade em Pesquisa) from Fundação Araucária de Apoio ao Desenvolvimento Científico e Tecnológico do Estado do Paraná (FAPPR) - the project was selected from a total of 800+ proposals submitted to the open call. Prof. Dr. Wehrmeister has been involved in various research projects funded by Brazilian Companies and R&D agencies.

Coffee Break + Poster Session 1

Poster Session 1 Exhibition List:

• Exploiting the Design of Time-to-Digital Converters - TDC
  Lesley Ferreira, Mateus Moreira, Barbara Souza, Sandro Ferreira, Filipe Baumgratz and Sergio Bampi
• Low Power 1.8 GHz Digitally Controlled Oscillator for IoT Applications
  Mateus B. Moreira, Lesley Ferreira, Bárbara Souza, Sandro B. Ferreira, Filipe Baumgratz and Sergio Bampi
• Approximate Sum of Absolute Transformed Differences Hardware Accelerator
  Matheus F. Stigger, Victor H. S. Lima, Leonardo B. Soares, Cláudio M. Diniz and Sergio Bampi
• Approximate Interpolation Filters for HEVC Targeting High-Definition Encoding in Real Time
  Rafael Silva, Ricardo Reis and Mateus Grellert
• Analysis of Hadamard Transform Coefficiente Pruning for Approximate SATD Calculation
  Victor H. S. Lima, Matheus F. Stigger, Leonardo B. Soares and Cláudio M. Diniz
• All-Digital Phase-Locked Loop for IoT Applications
  Barbara Souza, Lesley Ferreira, Mateus Moreira, Sandro Ferreira, Filipe Baumgratz and Sergio Bampi
• A sub-1mA Highly Linear Inductorless Wideband LNA with Low IP3 sensitivity to Variability for IoT Applications
  Arthur Liraneto T. Costa, Hamilton Klimach and Sergio Bampi

Tiago Balen - Universidade Federal do Rio Grande do Sul (UFRGS)
Reliability of Analog-to-Digital Interfaces of Mixed-Signal SoCs under Radiation and Electromagnetic Interference

Abstract:
Analog-to-digital converters (ADCs) are common blocks in control, instrumentation and communication systems, including the ones adopted in safety-critical and space applications. Therefore, as important as the correct functioning of computing units, is the reliability of analog-to-digital (AD) and digital-to-analog (DA) system interfaces. In this talk, the results of radiation and electromagnetic interference tests on data converters embedded in a programmable mixed-signal system-on-chip (whose processing element is an ARM Cortex M3 processor) are presented. Two popular architectures of ADCs are considered: Successive Approximation Register (SAR) and Sigma Delta (). A redundant scheme based on design diversity is applied and the devices are exposed to gamma radiation, heavy ions and significant electromagnetic fields. Fault injection experiments by emulation and spice simulation are also carried out. Results allow to evaluate the converters’ reliability besides compare the results among the different architectures and evaluate the applied fault tolerant techniques.

Short Bio:
Tiago Roberto Balen received his Electrical Engineering degree, in 2004, from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil. In 2006 and 2010, respectively he received the MSc degree and the PhD degree from UFRGS. In 2012, he received an important award from FAPERGS (Rio Grande do Sul State Research Fomentation Agency) for the innovative contributions of his PhD thesis. His research interests include analog and mixed-signal test, built-in-self test, programmable analog devices, fault tolerant circuits and radiation effects on electronic systems. In the past years, he has published more than 50 papers on these topics in important conferences and journals, receiving a "e;Best Paper Award"e; for one of his contributions. Currently, he is associate professor at the Electrical Engineering department and head of the graduate program on Microelectronics (PGMICRO) of the Federal University of Rio Grande do Sul (UFRGS).

Sorin Cotofana - TU Delft - Delft, The Netherlands
IEEE CASS Distinguished Lecturer
Talk 1: Energy Effective Graphene Based Computing

Abstract:
In this presentation we argue and provide Non-Equilibrium Green's Function Landauer formalism-based simulation evidence that in spite of Graphene's bandgap absence, Graphene Nanoribbons (GNRs) can provide support for energy effective computing.  We start by demonstrating that: (i) band gap can be opened by means of GNR topology and (ii) GNR's conductance can be mold according to some desired functionality, i.e., 2- and 3-input AND, NAND, OR, NOR, XOR, and XNOR, via shape and electrostatic interaction. Afterwards, we introduce a generic GNR based Boolean gate structure composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the gate inverted Boolean function, and, by properly adjusting GNRs' dimensions and topology, we design and evaluate by means of SPICE simulations inverter, buffer, and 2-input GNR based AND, NAND, and XOR gates. When compared with state-of-the-art graphene FET and CMOS based counterparts the GNR-based gates outperform its challengers, e.g., up to 6x smaller propagation delay, 2 orders of magnitude smaller power consumption, while requiring 1 to 2 orders of magnitude smaller active area footprint than 7nm CMOS equivalents. Finally, to get better inside in the practical implications of the proposed approach, we present Full Adder (FA) and SRAM cell GNR designs, as they are currently fundamental components for the construction of any computation system. For an effective FA implementation, we introduce a 3-input MAJORITY gate, which apart of being able to directly compute FA's carry-out is an essential element in the implementation of Error Correcting Codes codecs, that outperforms a 7nm CMOS equivalent Carry-Out calculation circuit by 2 and 3 orders of magnitude in terms of delay and power consumption, respectively, while requiring 2 orders of magnitude less area. The proposed FA exhibits 6x smaller delay, 3 orders of magnitude less power consumption, while requiring 2 orders of magnitude less area than a 7 nm FinFET CMOS counterpart. However, because of the effective carry-out circuitry, a GNR-based n-bit Ripple Carry Adder, whose performance is linear in the Carry-Out path delay, will be 108x faster than an equivalent CMOS implementation. The GNR-based SRAM cell provides a slightly better resilience to DC-noise characteristics, while performance-wise has a 3x smaller delay, consumes 2 orders of magnitude less power, and requires 1 order of magnitude less area than the CMOS equivalent. These results clearly indicate that the proposed GNR-based approach is opening a promising avenue towards future competitive carbon-based nanoelectronics.

Short Bio:
Sorin Cotofana (M'93-SM'00-F'17) received the MSc degree in Computer Science from the "Politechnica" University of Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focused on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 250 papers in peer-reviewed international journal and conferences, and received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), member of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems Senior Editorial Board (2016-2017), Steering Committee member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018), Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015), and IEEE Nano Council CASS representative (2013-2014) and has been actively involved as reviewer, Technical Program Committee (TPC) member, and TPC (track) and general (co)-chair, in the organization of numerous international conferences. He is currently Associate Editor in Chief and Senior Editor for IEEE Transactions on Nanotechnology and Associate Editor for IEEE Transactions on Computers. He is a Fellow IEEE member (Circuits and System Society (CASS) and Computer Society) and a HiPEAC member.

David J. Allstot - Oregon State University (OSU) - Corvallis, OR, USA
IEEE CASS Distinguished Lecturer
Switched-Capacitor Circuits: From Maxwell to the Internet of Things

Abstract:
The switched-capacitor technique has been used in high-volume data converters and signal processing ICs for more than three decades. It is also ubiquitous in RF transceiver circuits because it uses capacitors, which are area-efficient native devices in CMOS technologies, and MOSFETs operating as switches. The RF power amplifier dissipates a large fraction of the total power of a transceiver because of its low efficiency. Despite more than two decades of extensive research, the challenge of on-chip RF PAs with high efficiency in digital-friendly CMOS technologies has not been met. Switching PA topologies with relatively high efficiency have gained momentum, and relatively high output power is being delivered using power combining techniques. Supply regulation techniques have enabled higher efficiency when amplifying non-constant envelope modulated signals. The switched-capacitor RF power amplifier which meets many of the remaining challenges is described. Body-area-networks (BAN) that integrate multiple sensor nodes in portable and wearable bio-medical systems are revolutionizing healthcare. A typical BAN comprises several bio-signal and motion sensors and uses ultra-low-power short-haul radios in conjunction with nearby smart-phones or handheld devices (with GPS capabilities) to communicate via the internet with a doctor or other healthcare professional. Higher energy efficiency is critical to the development of feature-rich, wearable and reliable personal health-monitoring systems. The amount of data transmitted to the smart-phone increases as more sensors are added to the BAN. Because the energy consumed for RF transmission is proportional to the data rate, it is advantageous to compress the bio-signal at the sensor prior to digitization and transmission. This energy-efficient paradigm is possible using compressed sensing—a sampling theory wherein a compressible signal can be acquired using only a few incoherent measurements. For ECG signals, for example, large compression factors are achievable which means similar reductions in energy consumption. The second part of this talk overviews compressed sensing techniques and describes a switched-capacitor analog front-end for bio-signal acquisition.

Short Bio:
David J. Allstot holds a B.S., Engineering Science from University of Portland, Portland, OR, 1969, a M.S., Electrical and Computer Engineering from Oregon State University, Corvallis, OR, 1974 and a Ph.D., Electrical Engineering and Computer Science from University of California, Berkeley, CA, 1979. He has held several industrial and academic positions including the Boeing-Egtvedt Chair at the Univ. of Washington from 1999 to 2012 and Chair of EE from 2004 to 2007. In 2012 he was a Visiting Professor of EE at Stanford and from 2013 to 2016, he held a three-year appointment as the MacKay Professor in Residence in EECS at UC Berkeley. Since June 2017, he has been a Professor in EECS at Oregon State University. He has advised about 65 M.S. and 40 Ph.D. graduates, published more than 300 papers, and received awards for teaching and research including the 1980 IEEE W.R.G. Baker Award, 1995 and 2010 IEEE Circuits and Systems Society (CASS) Darlington Award, 1998 IEEE ISSCC Beatrice Winner Award, 2004 IEEE CASS Charles A. Desoer Technical Achievement Award, 2005 SRC Aristotle Award, 2008 Semiconductor Industries Association University Research Award, 2011 IEEE CASS Mac Van Valkenburg Award, and 2015 IEEE Trans. on Biomedical Circuits and Systems Best Paper Award. He has been active in service to the IEEE CASS and Solid-State Circuits Societies throughout his career.

Sorin Cotofana - TU Delft - Delft, The Netherlands
IEEE CASS Distinguished Lecturer
Talk 2: Beyond CMOS Boolean Gates Based Computing

Abstract:
For many decades, we are witnessing an on-going increase in Integrated Circuit (IC) performance due to: (i) advances in fabrication technology and (ii) improvements in computational paradigms. IC feature size reduction has been an important contributing factor to the dramatic increase in the processing power of logic and arithmetic circuits. However, it is generally accepted that, sooner or later, MOSFET-based circuits cannot be reduced further in (feature) size due to fundamental physical restrictions. Therefore, several emerging nano-technologies are currently being investigated, e.g., Single Electron Tunneling (SET) junctions, Magnetic Tunneling Junctions, Memristive devices, Nano Electro Mechanical FETs. Currently, there is a wide gap between the research on nano-scale devices and the research on their utilization in computer technology. Most of the community is attempting to mold emerging nano-devices to fit into the CMOS centric design methodology, i.e., is seeking a FET replacement nano-device. However, essentially speaking, these new nano-devices exhibit behaviors that are substantially different than that of the well-established MOS devices and if we are to fully utilize the potential of these emerging devices we should adapt the paradigms to their specifics. Moreover, inherent to very small devices are parameter variations and low reliability, which also fundamentally impact the way we design/program computer systems. Together with some other sources of variance, e.g., temperature and power supply variations, these parameter variations cause significant fluctuations in the time required by a part of a circuit to perform its computational task, which has to be dealt with at the circuit and architecture levels. In this presentation we first discuss nano-era specific challenges and opportunities one has to face and/or make use of, when designing and programming computation platforms. Then, we argue that traditional approaches, which are effective for CMOS, may not be that effective for emerging nano-devices. To make our case we address the following questions: (i) Should Boolean algebra always be the foundation on which digital hardware is built? (ii) Are nano-mechanical devices capable to contribute to energy consumption reduction? (iii) Can noise and ageing be embraced instead of suppressed and utilised in computation and reliability improvement? In this line of reasoning, we first introduce 3 SET based logic families: Single Electron Encoded Logic, which builds upon Threshold Logic, Electron Counting, and Brownian computing, which follow completely unorthodox paradigms. Subsequently, we present ultra-low power NEMFET based short circuit current free logic and its utilisation in power management and memory design. Finally, we briefly describe an Averaging Cell based fault tolerant structure, which relies on noise to take advantage of the Dynamic Stochastic Resonance phenomenon to increase its performance.

Short Bio:
Sorin Cotofana (M'93-SM'00-F'17) received the MSc degree in Computer Science from the "Politechnica" University of Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focused on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 250 papers in peer-reviewed international journal and conferences, and received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), member of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems Senior Editorial Board (2016-2017), Steering Committee member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018), Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015), and IEEE Nano Council CASS representative (2013-2014) and has been actively involved as reviewer, Technical Program Committee (TPC) member, and TPC (track) and general (co)-chair, in the organization of numerous international conferences. He is currently Associate Editor in Chief and Senior Editor for IEEE Transactions on Nanotechnology and Associate Editor for IEEE Transactions on Computers. He is a Fellow IEEE member (Circuits and System Society (CASS) and Computer Society) and a HiPEAC member.

Coffee Break + Poster Session 2

Poster Session 2 Exhibition List:

• Electrocardiograph with automatic gain adjustment using PGIAs
  Luís Eduardo Davoglio Estradioto, Arthur Christoff Koucher and Gabriel Marins da Costa
• Design of a Near-Threshold Digital Library at 0.3V in CMOS 28nm
  Rodrigo N. Wuerdig and Sergio Bampi
• Lighting Characterization Equipment
  A.C. Rossi, D.P.S. Junior, P.R.S. Sanches, M.S. Medeiros, M.A.B. Oliveira, A.C. Tonon, M.P. Hidalgo, M. Schimid, P.V.S. Magalhães and A.F. Muller
• Rate-Distortion and Complexity Comparison of HEVC and VVC Video Encoders
  Icaro Siqueira, Guilherme Correa and Mateus Grellert
• Analytic Modeling of 6T SRAM Bitcell State-Space Using Machine Learning
  Felipe R. B. Vianna and Raphael M. Brum
• Analysis of Magnetic Tunnel Junctions Behavior considering Single and Multi-Domain Free Layer Magnetization
  Paulo R. Klaudat and Raphael M. Brum
• Explaining failure mechanism of charge redistribution SAR ADCs under TID effects
  Lucas Meurer Lameira, Bruno Lau da Costa, Carlos Aguilera and Tiago Roberto Balen
• Improving Selective Fault Tolerance in GPU Register Files by Relaxing Register Criticality
  Márcio Gonçalves, Ivan Lamb, Raphael M. Brum and José Rodrigo Azambuja

IEEE Young Professionals Workshop - Industry Panel
What kind of engineer are companies looking forward to hire?

Abstract:
In the first IEEE Vision, Innovation and Challenges Summit, held in San Francisco, CA, USA in 2017, James Plummer, former Dean of Stanford University and and a professor of engineering, said that the engineers who will invent the future "will be a different breed of people than the engineers we educated in the 20th century". He also predicted that the undergraduate engineering education will radically change. In the brazilian academic scene, entrepreneurship-oriented education, innovative pedagogy, interdisciplinarity and many other concepts — or buzzwords? — are constantly heard in the discussions among professors, technicians and students. Several government agencies are funding projects to promote innovation in Engineering Education or outlining new directives for current and new undergraduate courses in the country. Given the new challenges ahead, we invited local companies in the field of microelectronics to help us answer the following question: "What kind of engineer are companies looking forward to hire?"

Short Bio:

Moderator: Prof. Renato P. Ribas, INF/UFRGS— Renato P. Ribas received B.S. and M.S. degrees in electrical engineering respectively from UFRGS, in 1991, and Unicamp, in 1994, Brazil, and Doctor degree in microelectronics from INPG, France, in 1998. Professor at Informatics Institute, UFRGS, since 2000. Post-Doctoral sabbatical year at UBC, Canada, in 2010/2011, and Chief Scientist at Nangate A/S, Denmark, in 2005/2006. He was president of the Brazilian Microelectronics Society and coordinator of the computer engineering course at UFRGS. His research interest includes VLSI system and circuit design, CAD development and new technologies for digital IC design.

Bernardo Culau - Director of Characterization, Silvaco—Bernardo is Director of Characterization at Silvaco. He joined Silvaco in 2018 as part of the acquisition of Nangate where he had worked for 9 years. At Nangate he developed EDA tools for library characterization and delivered standard cell library IP for multiple foundries and technology nodes. Bernardo holds Computer Engineering degrees from Universidade Federal do Rio Grande do Sul, Brazil and from Grenoble INP, France

Eric Ericson Fabris, Ph.D. - CTO / R&D Superintendent, CEITEC—Eric Fabris has a degree in electrical engineering (1988), a MSc. in electronic Instrumentation (1994) and PhD in Computer Science - Microelectronics (2005), both from the Federal University of Rio Grande do Sul. He is Associate Professor on leave at Engineering School at UFRGS since 1991. He has his main interest and technical focus in the design of Analog integrated circuits, mixed signals of low-power and communication systems architecture. Was technical coordinator of the Training Centers of the CI Program Brazil (2007-2016). He is a former President of the Brazilian Society of Microelectronics-SBMicro (Sep/2012 until Aug/2016). He was CEO of CEITEC Civil Association (April/2011 until December 2012). He currently is the CTO - Superintendent of products, research and development on CEITEC S.A. and also a Director of ABISEMI – Associação Brasileira de Semicondutores.

Alcides Costa - CEO and Co-founder, InPlace—Alcides started his career in 2005, developing tool training in Synopsys, Altera and Xilinx tools at NSCAD. He provided consulting services on multi-vendor digital IC design flows, targeting 350nm to 130nm technologies. From 2008 to 2011, Alcides led the Brazilian Program for developing IC designers in cooperation with Cadence Design System. He obtained credentials on Cadence tools and qualified more the 300 engineers in the Cadence digital IC design flow. Next, he managed the CEITEC Semiconductor CAD team, being co-responsible for the tape-out of IoT chips using mature technologies. Alcides received his bachelor degree in ECE from the Federal University of Rio Grande do Sul (UFRGS).