November 10, 2020
Horário	Palestrante
09:10	Opening Session
09:30	Massimo Alioto - Circuits and Architectures with Ultra-Wide Power Adaptation for Next-Generation Always-On Systems National University of Singapore (NUS), Singapore Abstract & Short Bio
10:30	Coffee Break
10:45	Erik Jan Marinissen - 3D Test and Design-for-Test Challenges and Solutions IMEC, Belgium Abstract & Short Bio
11:45	Lunch
14:00	José Gabriel Gomes - CMOS Image Sensors and Focal-Plane Image Processing Universidade Federal do Rio de Janeiro (UFRJ), Brazil Abstract & Short Bio
15:00	Opportunities within Circuits and Systems Society (CASS)
15:30	Coffee Break
15:45	Applying Approximate Computing to Energy-Efficiency Circuit Design Marcio Monteiro, Cristina Meinhardt UFSC Exploring Tree-Based Inference Engines for Low-Power Learning Applications Brunno Abreu, Mateus Grellert, Sergio Bampi UFRGS, UFSC An architecture of the sigmoid function by lookup table Daniel Gaio, Fabio Ramos UNIPAMPA Proposal of a pipelined architecture for the AV1’s arithmetic encoder block Tulio Bitencourt, Fábio Ramos, Sergio Bampi UFRGS, UNIPAMPA Hardware/Software co-design for CNN inference in FPGA devices based on YOLOv3-Tiny + XNOR-Net networks Welbert Castro, Fábio Ramos, Bruno Neves UNIPAMPA Low Power AV1 FME Interpolation Filters Exploring Approximate Computing William Kolodziejski, Robson Domanski, Luciano Agostini UFPel Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding Luiz Neto, Marcel Correa, Daniel Palomino, Luciano Agostini, Guilherme Correa UFPel A DBF Hardware architecture for the AV1 Decoder Roberta Palau, Eduardo Zummach, Jones Goebel, Guilherme Corrêa, Marcelo Porto, Luciano Agostini UFPel Energy/QoS-Aware Video Processing over Scalable NoC using Multi-Level Approximate Hardware Acceleration Wagner Penny, Daniel Palomino, Marcelo Porto, Bruno Zatt UFPel 4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding Jones Goebel, Matheus Jahnke, Daniel Palomino, Guilherme Correa, Luciano Agostini, Bruno Zatt and Marcelo Porto UFPel Dedicated Hardware Designs for the CDEF In Loop Filter to the AV1 Decoder Targeting 4K UHD Videos Eduardo Zummach, Roberta Palau, Jones Goebel, Luciano Agostini, Marcelo Porto UFPel A CTU based IME Approach for Multiple Block Sizes Processing in a Efficient Hardware Design Murilo Perleberg, Vladimir Afonso, Bruno Zatt, Marcelo Porto UFPel, IFSUL

November 11, 2020
Horário	Palestrante
09:30	Yann Deval - Radiation-Hardening-by-Design of CMOS Integrated Circuits. Application to Space Electronics Université de Bordeaux (IMS), France Abstract & Short Bio
10:30	Coffee Break
10:45	Krishnendu Chakrabarty - Functional Criticality Classification of Structural Faults in AI Accelerators Duke University, USA Abstract & Short Bio
11:45	Lunch
14:00	Dr. Marcelo de Souza - Adaptive RF Amplifiers dedicated to Wireless Communication Efficiency Enhancement Universidade Federal do Paraná (UFPR), Brazil Abstract & Short Bio
15:00	Coffee Break
15:15	Volatile and Non-Volatile Flip-Flops, an Overview Klaus Holler, Raphael Brum, Paulo Butzen UFRGS Soft Error and Half-Selection Evaluation of SRAM Cells Cleiton M. Marques, Cristina Meinhardt, Paulo F. Butzen UFRGS, UFSC Towards the Design of an Accumulator Based 8-bit Nonvolatile Processor Bruna Cagliari, Paulo Butzen, Raphael Brum UFRGS Digital-based analog processing in nanoscale CMOS ICs for IoT applications Pedro Toledo, Hamilton Klimach, Paolo Crovetti UFRGS, Polito-Italy Design of a Manufacturable Near-Threshold Time-to-Digital Converter Rodrigo Wuerdig, Filipe Baumgratz, Sergio Bampi UFRGS EVALUATING VIABILITY OF CMOS COMPLEX LOGIC GATES IN HIGH PERFORMANCE CIRCUITS Bruno Ferraz; Henrique Kessler; Vinícius Camargo UFPel Challenges on a Crossbar Magnetic Random Access Memory Project Bruno S. Zimmer, Paulo F. Butzen, Raphael M. Brum UFRGS Logic Aware Transistor Network Sizing for CMOS Supergates Henrique Kessler, Vinícius Camargo UFPel Mapping Critical Nodes of Mirror Full Adder Rafael Oliveira, Fabio da Silva, Ricardo Reis, Cristina Meinhardt UFSC, UFRGS APPROXIMATE SUBTRACTOR OPERATOR FOR LOW-POWER VIDEO CODING HARDWARE ACCELERATORS Rafael Ferreira,Luciano Agostini, Claudio Diniz, Bruno Zatt UFPel, UCPel Memory Profiling of H.266 Versatile Video Coding Standard Arthur Cerveira, Luciano Agostini, Bruno Zatt, Felipe Sampaio UFPel, IFRS

November 12, 2020
Horário	Palestrante
09:30	Matteo Reorda - In-field test for safety-critical automotive devices Polito, Italy Abstract & Short Bio
10:30	Coffee Break
10:45	Shrinivas Katkoori - Behavioral and RT-level Synthesis of Secure Hardware University of South Florida (USF), USA Abstract & Short Bio
11:45	Lunch
14:00	Lawrence Clark - The ASAP predictive PDK: History, assumptions, usage, and what to expect next Arizona State University (ASU), USA Abstract & Short Bio
15:00	Coffee Break
15:15	Algorithm Selection for Detailed Placement Using CNNs Renan Netto, José Luis Güntzel UFSC Routability-Driven Detailed Placement Using Reinforcement Learning Sheiny Fabre Almeida, Cristina Meinhardt, Laleh Behjat UFSC, Univeristy of Calgary - Canada Logic Function Optimization with Cartesian Genetic Programming Augusto Berndt, Brunno Abreu,Isac Campos,Jônata Carvalho,Mateus Grellert,Cristina Meinhardt UFSC, UFRGS Divide and Conquer to Enable SPR-MP Reliability Analysis in Complex Circuits Glória Claro, Rafael Schvittz, Paulo Butzen FURG, UFRGS Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults Marcio Goncalves, Fabio Benevenuti, Hector Munoz, Marcelo Brandalero, Michael Hubner, Fernanda Kastensmidt, Jose Azambuja UFRGS, Brandenbug University of Technology - Germany PROFILER FOR MOTORCYCLE RACERS Wendell Gasparoni, Bruno Neves UNIPAMPA Automatic Synthesis of Transistor Network Layouts for FDSOI Elias Ramos, Vitor Maciel, Germano Girondi, Ricardo Reis UFRGS Exploring the Impact of Soft Errors in Neural Networks Executing on Resource-constrained IoT Devices Geancarlo Abich, Luciano Ost, and Ricardo Reis UFRGS, Loughborough University - United Kingdom Contributions to OpenROAD from Abroad: Experiences and Learnings Mateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen and Ricardo Reis UFRGS PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications Mahdi Yektaei, M. B. Ghaznavi-Ghoushchi Shahed university - Iran

November 13, 2020
Horário	Palestrante
09:30	Pascal Vivet - 3D technology in heterogeneous systems: promises, reality and perspectives of technology and architecture for new computing paradigm CEA-LIST, France Abstract & Short Bio
10:30	Coffee Break
10:45	Aida Todri-Sanial - A Look Into Physical Modeling and Design for Carbon Nanotube based Circuits Université de Montpellier (LIRMM), France Abstract & Short Bio
11:45	Lunch
14:00	IEEE Young Professionals Workshop
15:30	Coffee Break
15:45	Closing Session
16:15	Social Event

Massimo Alioto - National University of Singapore (NUS), Singapore
Circuits and Architectures with Ultra-Wide Power Adaptation for Next-Generation Always-On Systems

Abstract:
Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the instantaneous performance requirement. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., higher-quality sensing, on-chip data analytics), while maintaining the consumption extremely low in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation beyond conventional voltage scaling. In this context, systems able to adapt to a wide performance-power range allow continuous operation and adjustment to the application power-performance profile. In this talk, new techniques that drastically extend the performance-power scalability of circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to a dynamic power-performance requirement are illustrated for several sub-systems, from digital circuits to memories, data converters, networks on chip, and others. As an orthogonal design dimension, “just-enough” adaptation to the application-level quality requirement is shown to further extend the performance-power range by an order of magnitude or more in prominent applications (e.g., vision, machine learning). Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.

Short Bio:
Massimo Alioto is with the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area and the FD-FAbrICS industry-sponsored lab on FD-SOI intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs CRL, University of Michigan Ann Arbor, University of California Berkeley, EPFL - Lausanne. He is author of 300+ publications on journals and conference proceedings, and four books with Springer, including the popular “Enabling the Internet of Things – from Integrated Circuits to Integrated Systems”, which is the first book published in the area of integrated system design for the edge of the Internet of Things. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies. He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto is/was a Distinguished Lecturer for the IEEE Solid-State Circuits and Circuits&Systems Society. He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2023, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.

Session Chair: Sergio Bampi, UFRGS, Brazil

Erik Jan Marinissen - IMEC, Belgium
3D Test and Design-for-Test Challenges and Solutions

Abstract:
Three-dimensional stacking of ICs has kept folks in both technology and design research busy for several years. This research has advanced to the point that virtually all semiconductor companies have now released or announced 3D-SIC products or are developing such products in stealth mode. No wonder, because 3D-SICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all these benefits can only materialize if 3D-SICs can be properly tested for manufacturing defects. In this presentation, I will review the main challenges related to test and design-for-test (DfT), and present solutions that we at imec, together with partners, have worked on in the recent past. The talk will cover (1) a generic 3D die stack model and associated tests, (2) probe access from external test equipment to dies or die stacks during the various steps of the stack assembly flow, (3) 3D-DfT architectures that provide test access internal to the die stack, and (4) cost modeling to determine optimized, cost-effective test flows. As founder and first chair of IEEE Std 1838-2019, I will of course also address this new 3D-DfT standard that was released in March 2020.

Short Bio:
Erik Jan Marinissen is scientific director at imec in Leuven, Belgium, the world-leading independent R&D center in nanoelectronics technology. His research on IC test and design-for-test covers topics as diverse as TSV-based 3D-stacked ICs, sub-10nm CMOS technology, silicon photonics, and STT-MRAMs. In addition, he is visiting researcher at Eindhoven University of Technology (TU/e), the Netherlands. Previously, he worked at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale. Marinissen holds an MSc degree in Computing Science (1990) and a PDEng degree in Software Technology (1992), both from TU/e. He is (co-)author of 275+ journal and conference papers and (co-)inventor of eighteen US/EP patents. Marinissen served as Editor-in-Chief of IEEE Std 1500TM-2005 on embedded core test access and as Founder and Chair (currently Vice-Chair) of IEEE Std 1838TM-2019 on 3D test access. Marinissen is founder of the workshops ‘Diagnostic Services in Network-on-Chips’ (2007-2011), ‘3D Integration Workshop’ (2009-2013), and the IEEE International Workshop on Testing Three-Dimensional Stacked ICs’ (2010-2015). He has been Program Chair of DDECS 2002, ETS 2006, 3D-TEST 2009-15, and DATE 2013, and General Chair of ETW 2003, DSNOC 2007-08, 3DIW 2009-10, and serves on numerous conference committees, including ATS, DATE, ETS, ITC, ITC-Asia, and VTS. He serves on the editorial boards of IEEE ‘Design & Test’ and Springer’s ‘Journal of Electronic Testing: Theory and Applications’. On its 50th anniversary, the IEEE International Test Conference (ITC) announced Marinissen to be the most-cited author of ITC papers over the 25-year period 1995-2019. Marinissen is (co-)recipient of the Most Significant Paper Awards at ITC 2008 and ITC 2010, Best Paper Awards at the Chrysler-Delco-Ford Automotive Electronics Reliability Workshop 1995 and the IEEE International Board Test Workshop (BTW) 2002, the Most Inspirational Presentation Award at the Semiconductor Wafer Test Workshop (SWTW) 2013, the HiPEAC Technology Transfer Award 2015, the SEMI Best ATE Paper Award 2016, the National Instruments’ Engineering Impact Award 2017, the IEEE Standards Association’s Emerging Technology Award 2017, Best Paper Award at the International Wafer-Level Packaging Conference (IWLPC) 2018, and the Best Design-Track Paper Award at the Design, Automation, and Test in Europe (DATE) Conference 2020. Marinissen is Fellow of IEEE, Golden Core Member of IEEE Computer Society, and serves as elected member of the IEEE Computer Society’s Board of Governors for the term 2019-2021. Marinissen has presented full- and half-day tutorials on Core- Based SOC Test, 3D-SIC Test, and Improving ATPG Test Quality at 3DIC, 3D-ASIP, DATE, ETS/ETW, ITC, ITC-Asia, and VTS, as well as numerous multi-day in-house company courses. During the span of his career, Marinissen has supervised 45+ international MSc and PhD students. Marinissen is member of the Patient Researchers Working Group of the Dutch Parkinson’s Disease Association.

Session Chair: Tiago Balen, UFRGS, Brazil

José Gabriel Gomes - Universidade Federal do Rio de Janeiro (UFRJ), Brazil
CMOS Image Sensors and Focal-Plane Image Processing

Abstract:
CMOS image sensors have become widely used in commercial and consumer imaging devices, which is partly due to reasonable fabrication cost, and partly due to modifications in fabrication technology that led to very high image quality. We start this presentation with a brief summary of the historical development of CMOS image sensors. Different pixel types and their input/output signals are described. We then point out that regular transistors, equal to those which are already used inside each pixel, can also be used for the hardware implementation of focal-plane image processing tasks beyond those related to the basic image capture. Typical benefits include communications bandwidth and hardware complexity reduction. Some intermediate storage or digital signal processing modules are eliminated. We then present some examples of systems and applications involving focal-plane image processing, including data compression, feature computation, high-dynamic-range imaging, and the biomorphic representation of imaging signals. We present a few concluding remarks about the application of deep convolutional neural networks to computer vision tasks, considering potential research opportunities related to focal-plane image processing.

Short Bio:
José Gabriel Rodríguez Carneiro Gomes graduated in Electrical Engineering at the Federal University of Rio de Janeiro (UFRJ) in 1999. He received the M.S. degree in Electrical Engineering from COPPE/UFRJ in 2000, and from University of California at Santa Barbara (UCSB) in 2003, and the Ph.D. degree in Electrical Engineering from UCSB in 2004. In 2006, he joined the Faculty of the Electronics and Computer Engineering Department at UFRJ, where he is currently an Associate Professor. Since 2007, he has also been with the Faculty of the Electrical Engineering Program at COPPE/UFRJ. He is interested in CMOS image sensors, image processing, data compression, and neural networks. He received the Young Researcher of Our State research grants from FAPERJ for terms 2009-2012 and 2015-2017. He and his co-authors received the Best Paper Award (Analog Design) at the 25th Symposium on Integrated Circuits and Systems Design in Brasilia, in 2012. He was a recipient of the IEEE Circuits and Systems Society Chapter-of-the-Year Award (Region 9, 2009).

Session Chair: Bruno Zatt, UFPel, Brazil

Yann Deval - Université de Bordeaux (IMS), France
Radiation-Hardening-by-Design of CMOS Integrated Circuits. Application to Space Electronics

Abstract:
This talk addresses some design tricks that allow a dramatic reduction of integrated circuit sensitivity to radiation effects. Both analog and digital circuits are here addressed. Redundancy, specific topology, system-level compensation: any combination is helpful as long as it allows avoiding the implementation of a specific - and thus hugely expensive - radiation- hardened technology. Besides, using a regular CMOS technology also allows bringing into play state-of-the-art building blocks from an up-to-date library, paving the way to the design of highly efficient integrated circuits, something a natively radiation-hardened technology denies.

Short Bio:
Prof. Yann DEVAL joined the University of Bordeaux in the Southwest of France in 1993, as an Assistant Professor, focusing on the design of analog ICs, RFICs, high-speed mixed-signal ICs, and high-reliability electronics. He pursues his researches within the IMS, the laboratory of Integration, from Material to System. In 1999 Dr. Deval became an Associate Professor and, in 2004, a Full Professor. From 2006 to 2010 he was the head of the IC design Group, and from 2011 to 2016 the head of the Devices, Circuits and Systems (DCS) Department. Since 2016, Dr. Deval is the director of IMS. This public research laboratory is composed of 150 Ph.D. students and 150 faculties, with the support of roughly 100 technicians, engineers and admin assistants.

Session Chair: Paolo Rech

Krishnendu Chakrabarty - Duke University, USA
Functional Criticality Classification of Structural Faults in AI Accelerators

Abstract:
The ubiquitous application of deep neural networks (DNN) has led to a rise in demand for artificial intelligence (AI) accelerators. For example, the Tensor Processing Unit from Googlebased on a systolic arrayand its variants are of considerable interest for DNN inferencing using AI accelerators. DNN-specific functional criticality analysis identifies faults that cause measurable and significant deviations from acceptable requirements. The criticality of faults can thus be used to guide test grading and quality assessment of AI accelerators at various stages of the product lifecycle. Fault-criticality assessment method can be used to target domain-specific use-cases—different models, e.g., AlexNet, GoogleNet, ResNet, etc., mapped to the accelerator for applications such as digit classification and pattern recognition. As the functional criticality of faults depends on the type of dataset, DNN model, and model-to-hardware mapping, individual catalogs containing lists of critical and benign faults can be pre-generated for every domain-specific use-case. These catalogs can then be used by the customer as a reference for assessing functional fault-criticality. This presentation will examine the problem of classifying structural faults in an systolic-array accelerator based on their functional criticality. We first analyze pin-level faults in the processing elements (PEs) of a systolic array. Simulation results for the LeNet network with 32-bit and 16-bit data paths applied to the MNIST dataset show that over 93% of the pin-level structural faults in a PE are functionally benign. We next analyze the impact of stuck-at faults in the netlist of the PE and present a two-tier machine-learning (ML) based method to assess the functional criticality of these faults. We address the problem of minimizing misclassification by utilizing generative adversarial networks (GANs). The two-tier ML/GAN-based criticality assessment method leads to less than 1% test escapes during functional criticality evaluation of structural faults, and the precise identification of a small number of critical structural faults in PEs.

Short Bio:
Krishnendu Chakrabarty is the John Cocke Distinguished Professor and Department Chair of Electrical and Computer Engineering (ECE), and Professor of Computer Science, at Duke University. He has held Visiting Professor positions and Chair Professorships at University of Tokyo (Japan), University of Bremen (Germany), Tsinghua University (China), National Tsinghua University (Taiwan) and National Cheng-Kung University (Taiwan). Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), the Semiconductor Research Corporation Technical Excellence Award (2018), and the Japan Society for the Promotion of Science (JSPS) Invitational Fellowship in the “Short Term S: Nobel Prize Level” category (2018). Prof. Chakrabarty’s current research projects include: design-for-testability of integrated circuits and systems (especially 3D integration and system-on-chip); microfluidic biochips; hardware security; machine learning for eHealth; AI accelerators and neuromorphic computing systems. He is a Fellow of ACM, IEEE, AAAS, and a Golden Core Member of the IEEE Computer Society.

Session Chair: Ricardo Jacobi

Dr. Marcelo de Souza - Universidade Federal do Paraná (UFPR), Brazil
Adaptive RF Amplifiers dedicated to Wireless Communication Efficiency Enhancement

Abstract:
Wireless communication systems allow exploring information in complexenvironments by means of portable devices, whose main restriction is battery life.Once battery development does not follow market expectations, several efforts havebeen made in order to reduce energy consumption of those systems. Furthermore,radio-frequency systems are generally designed to operate as single-mode circuits,specified for RF link worst-case scenario. However, this scenario may occur in a smallamount of time, leading to energy waste in the remaining periods. The research ofadaptive radiofrequency circuits and systems, which can configure themselves inresponse to input signal level in order to reduce power consumption, is of interest andimportance. The Low Noise Amplifier (LNA) stands as critical elements, both on thechain performance and power consumption. In the past some techniques forreconfigurable LNA design were proposed and applied. Nevertheless, most of them areapplied to gain control, ignoring the possibility of linearity and noise figure adjustment,in order to save power. In addition, those circuits consume great area, resulting in highproduction costs, or they do not scale well with CMOS. This lecture aims todemonstrate the feasibility and advantages in using a digitally controlled LNA in an RFreceiver in order to save area and power consumption.

Short Bio:
Marcelo de Souza received the B.S. degree in Electrical Engineering, in 2004 and the M.Sc. degree in Electronic Devices in 2008, both from the Federal University of Paraná, Brazil and the Ph.D. degree in Electronics in 2016 in a partnership from the Technological Federal of Paraná, Brazil and University of Bordeaux, France. Since 2019, he is Associate Professor at the Department of Electrical Engineering of Federal University of Parana (UFPR) and member of the Group of Integrated Circuits and Systems (GICS). His research interests include RF/analog IC and RF system design for wireless communication.

Session Chair: François Rivet

Matteo Reorda - Polito, Italy
In-field test for safety-critical automotive devices

Abstract:
The strict dependability requirements posed by the current regulations and standards for safety-critical systems adopted in the automotive domain strongly impact the design and test solutions to be adopted. In particular, they require effective solutions not only for end-of-manufacturing test, but also for in-field test, i.e., for the tests which are performed while the system is already in the operational phase. This lecture will introduce the key goals, the current solutions and best practices, the future challenges of high quality in-field test. Specialized techniques and industrial standards for in-field testing of complex ICs are introduced. The reuse for in-field test of design for test structures and test data developed for end-of-manufacturing test is discussed, including the limitations and research challenges. Structural test methods can be complemented by functional test methods; hence, special emphasis will be devoted to overview state-of-the-art and leading edge research for functional testing.

Short Bio:
Matteo SONZA REORDA took the MS degree in Electronics in 1986 and the PhD degree in Computer Engineering in 1990, both from Politecnico di Torino (Italy). Since 1990 he is with the Dept. of Control and Computer Engineering of the Politecnico di Torino, where he currently is a Full Professor and leads a research group working on test and fault tolerant design of ICs and systems. He published more than 400 papers on these topics, and is involved in several research projects with companies and public bodies. He is a Fellow of IEEE.

Session Chair: José Rodrigo Azambuja

Shrinivas Katkoori - University of South Florida (USF), USA
Behavioral and RT-level Synthesis of Secure Hardware

Abstract:
The tremendous computing capabilities of the modern nanometer-scale Integrated Circuit (IC) have fueled the “silicon” age revolution. However, the complexity of IC design changed the landscape of the globalized electronics supply-chain into horizontal business model. Unfortunately, due to the involvement of multiple parties, IC supply-chain has led to several exploits including IC subversion. Hence, it is important to integrate security mechanisms inexpensively and efficiently during the early stage of IC design. We will present two defense-via-synthesis techniques and an analytical framework to improve hardware security assuming the potential capabilities of an attacker. First, we will discuss Register Transfer Level (RTL) obfuscation mechanism during behavioral synthesis. We embed multiplexers on non-critical paths for obfuscated RTL design followed by design lockout and camouflaging. This technique hardens the RTL IP against Reverse Engineering to a great extent. Second, we present an analytical estimation framework to localize Hardware Trojan (HT) in RTL design. We characterize arithmetic module architectures and propagate them during technology mapping to identify suitable modules of least rare triggering and better design parameters. Third, we desig monitor to capture original RTL controller behavior and prevent code-injection and code-reuse attacks and preserve the Control-Flow Integrity (CFI).

Short Bio:
Srinivas Katkoori is a Computer Science and Engineering faculty at the University of South Florida (USF), Tampa, FL. His research group has been actively conducting research on related topics such as low power digital VLSI design, reliable system design, Internet-of-Things (IoT), smart embedded systems, smart transportation, smart healthcare, etc. Dr. Katkoori has directed 15 doctoral dissertations and 41 Master’s Theses in the general discipline of Embedded Systems Design and Optimization. Dr. Katkoori serves on technical committees of several VLSI and embedded conferences and is a peer reviewer for many smart embedded systems journals and conferences. To date, he published over 125 peer-reviewed journal and conference papers. Three papers he has co-authored were nominated for best paper awards at 2003 ASP-DAC, 2014 IFIP/IEEE VLSI SOC, and 2019 AsianHOST conferences. Among notable professional service, Dr. Katkoori served on ACM SIGDA Board (2010- 2013) as Treasurer, as an Associate Editor of IEEE Transactions on VLSI (2006-10), and since 2015, he is serving as the vice-chair of IFIP Working Group 10.5 on Design and Engineering of Electronic Systems. Dr. Katkoori served as the General Chair of the 2019 2nd IFIP IoT Conference and 2020 IEEE International Symposium of Electronic Systems. Dr. Katkoori received his Ph.D. degree from the University of Cincinnati in 1998. He is a senior member of ACM and IEEE.

Session Chair: Luciano Ost

Lawrence Clark - Arizona State University (ASU), USA
The ASAP predictive PDK: History, assumptions, usage, and what to expect next

Abstract:
Commercial libraries and process design kits (PDKs) are often difficult to obtain for academic use, and access to quality physical layouts is even more restricted. Moreover, the requisite NDAs are problematic for university classes and make sharing results difficult. Finally, the sheer complexity of design rules can distract from the key points. This talk will include a description of the development of a realistic PDK for academic use, including the background and assumptions. Developed before the 7nm (N7) node was released by foundries, the predictive ASAP7 PDK was developed from research of basic tool limitations using our design expertise and design/technology co-optimization. The predictions were based on publicly disclosed information regarding the continually improving lithography, as well as our estimates of what would be available at N7. For the most part, these assumptions have been accurate, albeit aggressive in light of the initial commercial offerings. Specifically, the assumption of numerous layers using extreme ultraviolet (EUV) lithography has varied considerably by foundry. The background and impact on design technology co-optimization (DTCO) for standard cells and static random access memory (SRAM) will also be discussed in the context of building realistic designs using the PDK. Practical vs. academic assumptions in the industry and PDK assumptions will also be discussed, including where the PDK simplifications differ from what we expect from real processes. The talk will finish up with a description of enhancements to expect in standard cell and memory offerings as well as in a forthcoming 5nm predictive PDK (ASAP5).

Short Bio:
Lawrence T. Clark received the B.S. degree in computer science, the M.S. degree in electrical engineering, and the Ph.D. degree in electrical engineering in 1984, 1987, and 1992, respectively. Prior to earning his Ph.D. he was with Intel Corporation as a test engineer and VLSI Technology Inc., performing PC chipset design. In 1992, he joined Intel Corporation, where he contributed to the Pentium, Itanium, and XScale microprocessor designs, compact modeling, and CMOS imager projects. He worked on and or supervised logic and memory designs from the 0.6m through the 90nm process generations, including the process development vehicle for a flash+logic process. Most recently, he was a Principal Engineer and Circuit Design Manager on the XScale efforts, where he led the development of numerous dynamic and standby (drowsy) power saving modes. He joined Arizona State University (ASU), Tempe, AZ, USA, in 2004, as an Associate Professor, and held the rank of Professor from 2009 until August 2017. There, Prof. Clark supervised the research of 30 M.S. and 14 Ph.D. graduates. That work included over 20 successful test chips on 130nm through 12nm process generations. He is now an Emeritus Professor there. From 2009 to 2014, he was also with SuVolta Inc. as Chief Architect. Dr. Clark has authored/co-authored over 140 refereed technical papers, 10 book chapters, and has been awarded over 130 patents. As principal at LTC Design LLC, he has consulted for numerous companies and law firms. Dr. Clark received the Intel Achievement Award for the record-breaking XScale processor performance and low power. He is a member of the Association for Computing Machinery. He has been an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II, Guest Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I, and twice for the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He has been on the technical committees for numerous IEEE conferences.

Session Chair: Cristina Meinhardt

Pascal Vivet - CEA-LIST, France
3D technology in heterogeneous systems: promises, reality and perspectives of technology and architecture for new computing paradigm

Abstract:
The evolution of CMOS technology has shown his limits in terms of continuous scaling. In order to pursue the evolution of micro-electronic systems, with more functions, more memory, data treatment capability more tightly integrated, the integration of system can continue using heterogeneous partitioning, and this by using 3D integration technologies. These 3D technologies enables to partition and assemble a complete system, while offering function specialization, cost reduction, form factor reduction, communication energy reduction within the system, etc. The presentation will give an overview of available 3D technologies, with associated architectures and applications, and the possibility of new breakthrough architectures. In a more detailed manner, it will be presented recent outcomes from CEA on chiplet system design, on 3D imagers, and finally on compute in memory architecture.

Short Bio:
Pascal Vivet is Scientific Director of the Digital Systems a,d Integrated Circuits Division in CEA-LIST, Grenoble, France. He received his PhD from Grenoble Polytechnical Institute in 2001, designing an asynchronous microprocessor. After 4 years within STMicroelectronics, he joined CEA-Leti in 2003 in the digital design lab. His research interests covers wide aspects of circuit and system level design, ranging from system integration, multi-core architecture, Network-on-Chip, energy efficient design, related CAD design aspects, and in strong links with advanced technologies such as 3D integration, Non-Volatile-Memories, photonics. He was project leader on 3D circuit design and integration since 2011. He participates to various TPC such as ASYNC, DATE, 3DIC, ISLPED conferences. He served as a member of the organizing committee of the 3D workshops series at DATE from 2013 to 2015, and to the D43D workshops since 2011. He has authored and co-authored more than 100 papers and holds several patents in the field of digital design. He co-authored a book chapter on “3D Integration in VLSI Circuits: Implementation Technologies and Applications”.

Session Chair: Fernando Moraes

Aida Todri-Sanial - Université de Montpellier (LIRMM), France
A Look Into Physical Modeling and Design for Carbon Nanotube based Circuits

Abstract:
This talk aims to give an in-depth look into using carbon nanotubes as back-endof-line interconnects from process, modeling to physical design. The talk is organized into two parts. The first part provides an in-depth overview of the process and growth of carbon nanotubes and their resistance measurements. In the second part, the talk is dedicated to investigating carbon nanotubes for digital logic cells such as interconnects for signal, power and ground interconnect material. Due to the low-temperature growth, carbon nanotubes inherit a lot of defects that worsen its electrical resistance and ballistics transport. We investigate the doping of CNTs and show both experimental and simulations results of doped CNTs and their improved resistance. We compare the performance, power and area metrics of digital logics cells with conventional copper and carbon nanotube interconnects (undoped and doped) to highlight the advantages and limitations of carbon nanotube BEOL interconnects.

Short Bio:
Aida Todri-Sanial received the B.S. degree in electrical engineering from Bradley University, IL in 2001, M.S. degree in electrical engineering from Long Beach State University, CA, in 2003 and a Ph.D. degree in electrical and computer engineering from the University of California, Santa Barbara, in 2009. She is currently a Research Director for French National Council of Scientific Research (CNRS) attached to Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM). Previously, she was an R&D Engineer for Fermi National Accelerator Laboratory, IL. She has also held summer and visiting research positions at Mentor Graphics, Cadence Design Systems, STMicroelectronics and IBM TJ Watson Research Center. Her research interests focus on nanometer-scale issues in high-performance VLSI design with emphasis on power, thermal, signal integrity, and reliability issues as well as on circuits and systems for emerging technologies and nanomaterials. She has co-authored more than 100 publications on VLSI design area and emerging technologies. Dr. Todri-Sanial was a recipient of John Bardeen Fellow in Engineering in 2009, CNRS Prime d’Excellence Scientifique in 2012, ACM Distinguished Speakers 2016-2018, CNRS Bronze Medal in 2016, and ACM SIGDA Meritorious Service Award in 2020. She serves as Technical Program Committee member for IEDM, DAC, DATE, ISVLSI, NEWCAS, GLSVLSI, ISQED, and EDSSC. She is Associated Editor for IEEE Transactions on VLSI, Journal of Microelectronics Reliability and Microelectronics Journal.

Session Chair: Omar Paranaiba

Organization

General Chair:

José R. Azambuja (UFRGS)

Bruno Zatt (UFPel)

Program Chairs:

Ricardo Reis (UFRGS)
Alexandra Zimpeck (UCPel)

Poster Session Chair:

Fábio Ramos (Unipampa)
Mateus Grellert (UFSC)

Finance Chair:

Paulo Butzen (UFRGS)
Claudio Diniz (UCPel)

Streaming Chair:

Raphael Brum (UFRGS)

Publication Chair:

Rafael Schvittz (FURG)

Past Events

IEEE CASS Workshop 2008
IEEE CASS Workshop 2011
IEEE CASS Workshop 2012
IEEE CASS Workshop 2013
IEEE CASS Workshop 2015
IEEE CASS Workshop 2016
IEEE CASS Workshop 2017
IEEE CASS Workshop 2018
IEEE CASS Workshop 2019

Contact

Universidade Federal do Rio Grande do Sul
Instituto de Informática
Av. Bento Gonçalves, 9500
90650-001 - Porto Alegre, RS - Brazil

Final Program

Massimo Alioto - National University of Singapore (NUS), Singapore Circuits and Architectures with Ultra-Wide Power Adaptation for Next-Generation Always-On Systems

Erik Jan Marinissen - IMEC, Belgium 3D Test and Design-for-Test Challenges and Solutions

José Gabriel Gomes - Universidade Federal do Rio de Janeiro (UFRJ), Brazil CMOS Image Sensors and Focal-Plane Image Processing

Yann Deval - Université de Bordeaux (IMS), France Radiation-Hardening-by-Design of CMOS Integrated Circuits. Application to Space Electronics

Krishnendu Chakrabarty - Duke University, USA Functional Criticality Classification of Structural Faults in AI Accelerators

Dr. Marcelo de Souza - Universidade Federal do Paraná (UFPR), Brazil Adaptive RF Amplifiers dedicated to Wireless Communication Efficiency Enhancement

Matteo Reorda - Polito, Italy In-field test for safety-critical automotive devices

Shrinivas Katkoori - University of South Florida (USF), USA Behavioral and RT-level Synthesis of Secure Hardware

Lawrence Clark - Arizona State University (ASU), USA The ASAP predictive PDK: History, assumptions, usage, and what to expect next

Pascal Vivet - CEA-LIST, France 3D technology in heterogeneous systems: promises, reality and perspectives of technology and architecture for new computing paradigm

Aida Todri-Sanial - Université de Montpellier (LIRMM), France A Look Into Physical Modeling and Design for Carbon Nanotube based Circuits