Sergio Bampi
UFRGS – PGMICRO, Porto Alegre (RS)
Sergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics mixed-signal design fields at the Informatics Institute, member of the faculty since 1986. He served as Graduate Program Coordinator (PGMICRO, 2003-2007), head of research group and projects, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He is a former member of HP Inc. technical staff, and a visiting research faculty at Stanford University (1998-99) in the USA. His research interests are in the area of IC design, ultra-low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing, RF CMOS design and mixed signal IC designn for IoT. He has co-authored more than 440 papers in these fields and in MOS devices and EDA. He is a senior member of IEEE, SBC, and SBMICRO societies. He was Technical Program Chair of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Workshops and Conferences.
Near-Threshold CMOS Circuits: Frontiers in Ultra-Efficient Analog and Mixed-Signal CMOS Integrated Circuits
Segunda, 26 de Abril as 10:00
Resumo:
CMOS is an unbeatable, low-cost, and flexible technology to make the internet of “everything” (IoT) possible. Autonomic devices require ultra-low (UL) energy operation over their lifetime. This Talk stimulates system-level and circuit-level design approaches for IoT nodes, as sensing, mixed-signal and RF modules are essential for these UL-power gadgets. The nano-power range which is achievable in deca-nanometer CMOS at near-VT requires very specific logic design techniques to be applied in digital logic. This talk addresses a method to design CMOS digital circuits for a wide dynamic range of VFS, and targets near-threshold for best CMOS energy-efficiency. Maximizing energy efficiency by 50X to 100X (in energy/operation) is possible for circuits which tolerate ultra-wide frequency scaling (from hundreds of KHz to GHz ) in their system operating modes. The results in CMOS were obtained using the minimal cycle time achievable at each supply voltage, down to very low 200 mV supplies. The strategy for transistor sizing in digital cells and static noise margin maximization at near-VT will also be addressed in the talk. Recent mixed-signal CMOS approaches, with solely digital gates to implement ultra-efficient OTAs will also be shown, as a new approach to process low-frequency analog signals.