Ricardo Reis and Leonardo Brendler - UFRGS, Brazil
Circuit Level Design Methods to Mitigate Soft Errors
Abstract:
The mitigation of soft errors (SE) should be considered in all design abstraction levels, from a high-level to the physical one. This talk will discuss the efficiency of mitigation techniques to decrease the soft error susceptibility on the circuit/physical design levels considering a 7-nm FinFET technology. Simulations were performed at nominal and near-threshold operations. The transistor reordering putting the serial transistors as far as possible to the output is not favorable to mitigate the soft error susceptibility. For example, the AOI21 cell is 20% more robust to soft errors if the standard version is kept in the design. The gains of this technique are more significant for lower LETs. The logic multi-level design improves over 45% on average the SET results for the cells evaluated. The LETth considering the work-function fluctuation (WFF) impact is smaller than the LETth at ideal conditions. That is, due to WFF, a smaller amount of energy transferred by the particle is required to cause a disturbance in the circuit. When decoupling cells are adopted in the design, the soft error susceptibility decreases around 24.5%, 23.7%, and 11.4% for LETs equal to 15, 20, and 58MeV.cm2.mg-1, respectively, in our test cases. Although the design of FinFET gates connecting decoupling cells in the output is better to improve the SE susceptibility, larger SET pulses were verified mainly under higher LET levels. The results show that a design using a sleep transistor or Schmitt Trigger is very promising for soft error mitigation. The three logic cells evaluated become free of faults (no events seen at gate output) using these techniques, independently of the LET, input vector, or core voltage employed in the design.
Short Bio:
Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, and 2018, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. Member of IEEE CASS BoG and IEEE CEDA BoG. IFIP Fellow Award.
Leonardo H. Brendler received the B.S. degree in Computer Engineering and the M.S degree in Microelectronics from the Federal University of Rio Grande do Sul, Porto Alegre, Brazil, in 2018 and 2020, respectively. He is currently pursuing a PhD degree in Microelectronics in an international joint supervision between the Federal University of Rio Grande do Sul, Brazil, and the Université de Bordeaux, France, in partnership with the IMS Laboratory. His research interests include digital design, reliability on nanotechnologies, fault tolerant circuits and radiation effects on electronic systems.